Substrate-Free LED Chip Packaging Without Wire Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LED devices face challenges with large size due to wire-bonding structures and high manufacturing costs associated with flip-chip techniques, which require precise alignment and conductive traces.
Innovation Solution
A substrate-free LED device design featuring LED chips with electrode assemblies on the second surface, an electric circuit layer assembly on the second surfaces of the LED chips, and an encapsulating layer that exposes the circuit layer for electrical connection, eliminating the need for wire bonding and reducing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding structure is used to connect LED chips to electrodes, then electrical connection is achieved, but device size increases
Solution Approach 1:
The patent extracts and eliminates the wire-bonding structure from the LED device. Instead of using separate wire bonds to connect LED chips to electrodes, the invention integrates the electrical connection function directly into the package substrate through conductive traces, removing the unnecessary wire-bonding components and reducing device size.
Solution Approach 2:
The patent merges the electrical connection function with the package substrate structure. The conductive traces are integrated directly into the package substrate, combining the substrate's mechanical support function with the electrical interconnection function, thereby eliminating the need for separate wire-bonding structures.
2Area of stationary object
If flip-chip technique is used to bond LED chips to conductive traces, then device dimension is reduced, but manufacturing cost increases due to precise alignment requirements
Solution Approach 1:
The patent segments the electrical connection function into multiple conductive traces distributed across the package substrate. This segmentation allows for more flexible layout designs and reduces the need for precise one-to-one alignment between LED chips and conductive traces, thereby lowering manufacturing complexity and cost.
Solution Approach 2:
The patent changes the geometric parameters and spatial arrangement of conductive traces on the package substrate to optimize both device dimension and manufacturability. By adjusting trace width, spacing, and routing patterns, the design achieves compact size while maintaining ease of manufacturing through standard PCB fabrication processes.
Data Source
AI summary
A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.