Semiconductor Package Substrate Holes Eliminate Molding Voids
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Solution Overview
Problem
In semiconductor packages with a chip-on-chip (COC) structure, voids often form between semiconductor chips due to the flip chip bonding method, which can lead to reliability issues and complicate the manufacturing process.
Innovation Solution
A semiconductor package design that includes a package substrate with holes to facilitate the formation of a molding layer, which covers the semiconductor chips and fills the space between them, eliminating the need for an underfill resin layer and simplifying the manufacturing process by ensuring no voids are present between the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a flip chip bonding method is used to mount semiconductor chips, then high performance and high speed are achieved, but voids form between the semiconductor chips
Solution Approach 1:
The patent removes the underfill resin layer from the package structure. By eliminating this intermediate layer, the design achieves direct bonding between semiconductor chips and substrate, preventing void formation while maintaining high-speed signal transmission through improved electrical connectivity and reduced parasitic effects
Solution Approach 2:
Instead of using an underfill resin layer to fill gaps and improve reliability (conventional approach), the patent inverts the approach by completely removing the underfill layer and achieving reliability through direct bonding and optimized chip-substrate contact, thereby eliminating the source of void formation
2Reliability
If an underfill resin layer is used to fill space between chips, then voids are prevented, but the manufacturing process becomes more complex
Solution Approach 1:
The patent extracts and eliminates the underfill resin layer from the package structure. This removal simplifies the manufacturing process by eliminating the steps required to apply, align, and cure the underfill resin, while simultaneously preventing void formation through direct chip-to-substrate bonding
Solution Approach 2:
The patent merges the functions of the underfill resin layer into the direct bonding interface between the chip and substrate. By eliminating the intermediate layer and optimizing the direct contact interface, the design achieves both void prevention and process simplification through functional integration
3Quantity of substance
If multiple semiconductor chips are stacked in a COC structure, then memory capacity increases, but voids form between the stacked chips
Solution Approach 1:
The patent removes the underfill resin layer from multi-chip stacked structures. By eliminating this layer at each bonding interface in the stack, the design prevents void formation between stacked chips while maintaining high memory capacity through direct bonding of multiple chips to the substrate
Data Source
AI summary
Disclosed are semiconductor packages and methods of forming the same. In the semiconductor packages and the methods, a package substrate includes a hole not overlapped with semiconductor chips. Thus, a molding layer may be formed without a void.