Substrate-Integrated Capacitors for Vertical Power Delivery

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Solution Overview

Problem

Existing flip chip packages face challenges with RC signal delays and poor device density due to the use of decoupling capacitors with lateral power delivery and signal routing, which limits their effectiveness in suppressing power supply noise.

Innovation Solution

The integration of capacitors within the package substrate core for vertical power delivery, along with the use of thin-film capacitor structures and sealed capacitors, allows for efficient power delivery and noise filtering without the limitations of lateral routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If decoupling capacitors with lateral power delivery are used in flip chip packages, then power supply noise filtering is achieved, but RC signal delays increase and device density decreases

Engineering Contradiction:
Improvepower supply noise filteringVSAvoidRC signal delays
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from lateral (2D) power delivery through surface-mounted capacitors to vertical (3D) power delivery through substrate-integrated capacitors. The capacitor structures are embedded within the substrate core, with top and bottom electrodes connected to power and ground planes respectively, enabling power delivery in the vertical dimension rather than lateral routing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges the capacitor structures with the substrate core itself, making the substrate serve dual functions as both the mechanical support structure and the capacitor housing. The capacitor electrodes are formed as integral parts of the substrate layers, combining what were previously separate components into a unified structure.

Inventive Principle:
Principle #5Merging (Combining)

2Power

If decoupling capacitors are placed on the surface of the package, then power delivery is achieved, but device density is reduced due to占用 surface area

Engineering Contradiction:
Improvepower deliveryVSAvoiddevice density
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent nests the capacitor structures within the substrate core, placing them inside the three-dimensional volume of the substrate rather than on its surface. The capacitor electrodes are embedded between substrate layers, utilizing the internal volume of the substrate to house capacitor structures that would otherwise occupy valuable surface area.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent moves capacitor placement from the two-dimensional surface plane to the three-dimensional internal volume of the substrate. By embedding capacitors within the substrate core and utilizing vertical stacking, the design frees up surface area for additional active devices while maintaining power delivery capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If lateral signal routing through capacitors is used, then noise filtering is achieved, but signal transmission speed decreases due to RC delays

Engineering Contradiction:
Improvenoise filteringVSAvoidsignal transmission speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent changes the signal routing path from lateral (horizontal) to vertical by embedding capacitors within the substrate core. The vertical arrangement shortens the current path length through the capacitor structure, reducing the RC time constant and enabling faster signal transmission while maintaining noise filtering effectiveness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12288756B2Semiconductor package with integrated capacitors
Publication Date: 2025.04.29 CHIPLETZ INC
  • US12288756B2 patent drawing
  • US12288756B2 patent drawing
  • US12288756B2 patent drawing

AI summary

In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.