Substrate Integrated Inductor with Composite Magnetic Resin
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Solution Overview
Problem
The existing solutions for CPU voltage regulators, which rely on external inductive elements, face limitations in design flexibility and performance due to size and placement constraints, especially in low-profile package architectures, leading to decreased inductor performance as component sizes scale.
Innovation Solution
Integrating a composite magnetic inductor directly into the semiconductor substrate by depositing magnetic composite resin layers between conductive layers during the substrate manufacturing process, eliminating the need for external inductors and allowing for larger, more efficient inductors that can be designed to complement other substrate components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external inductive elements are used for CPU voltage regulators, then inductor performance can be maintained, but design flexibility and placement options are limited
Solution Approach 1:
The patent merges the inductor with the substrate by integrating magnetic composite resin layers and conductive layers directly into the substrate structure. This combination eliminates the need for separate external inductors while maintaining inductor performance and enabling flexible placement within the substrate architecture.
Solution Approach 2:
The patent transitions from three-dimensional external inductor components to a two-dimensional integrated structure within the substrate layers. By embedding the inductor functionality within the substrate's planar structure, the design achieves both performance maintenance and enhanced placement flexibility.
2Area of stationary object
If inductive elements are placed beneath the CPU package, then space on motherboard is freed, but inductor performance decreases
Solution Approach 1:
The patent combines the inductor with the substrate structure, allowing the inductor to be positioned in optimal locations within the substrate rather than being constrained to placement beneath the CPU package. This integration maintains inductor performance while still achieving space efficiency.
3Productivity
If component sizes are scaled down, then integration density increases, but inductor performance decreases
Solution Approach 1:
The patent segments the inductor into multiple thin layers (magnetic composite resin layers and conductive layers) that can be stacked vertically within the substrate. This segmentation allows the inductor to maintain adequate size and performance while fitting within the constrained space of scaled-down package architectures.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple thin layers to create the inductor structure. This approach allows the inductor to achieve sufficient size and performance characteristics without increasing the planar footprint, thereby maintaining integration density while improving inductor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, enhances inductor performance, and increases design flexibility, enabling more reliable and efficient power distribution systems within the CPU package.
Implementation Method 1
at least one composite magnetic inductor. The composite magnetic inductor includes at least one composite magnetic resin layer
Data Source
AI summary
A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.