Substrate-Integrated Components for Microelectronic Package Thermal and EMI Management
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Solution Overview
Problem
Legacy microelectronic packages face challenges in heat extraction from the top of RF dies due to insufficient thermal paths, increased package area from wirebonds, and reduced space for components due to 2D integration schemes, which are inadequate for stringent performance requirements.
Innovation Solution
The use of wafer reconstitution, flip-chip dies, through-mold vias, and substrate-integrated components with thick and thin redistribution layers for high-Q inductor integration, along with mold interconnects for EMI shielding, reduces z-height and X-Y area, and enhances thermal and crosstalk parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebonds are used to couple dies, then electrical connection is achieved, but package area increases
Solution Approach 1:
The patent removes wirebonds from the package structure entirely, replacing them with substrate-integrated interconnects. The dies are directly coupled to the substrate using integrated interconnect structures, eliminating the need for separate wirebond connections and thereby reducing package area while maintaining electrical connectivity.
Solution Approach 2:
The patent merges the electrical interconnection function with the substrate structure itself. The substrate-integrated interconnects combine the substrate's mechanical support role with the electrical connection role, eliminating the need for separate wirebond components and reducing overall package area.
2Ease of manufacture
If 2D integration schemes are used, then manufacturing is simplified, but space for components is reduced
Solution Approach 1:
The patent transitions from 2D integration to 3D integration by stacking multiple functional layers vertically within the substrate. Through-mold vias enable vertical interconnects between layers, allowing components to be arranged in three dimensions rather than confined to a single plane, thereby increasing component space while maintaining manufacturing feasibility.
3Quantity of substance
If conventional substrate integration is used, then component density increases, but thermal extraction from die top is insufficient
Solution Approach 1:
The patent segments the thermal management function into separate thermal vias that are distributed throughout the substrate. These thermal vias create dedicated thermal pathways from the die top through the substrate to heat sinks or thermal management structures, separating thermal extraction from electrical interconnection functions while maintaining high component density.
4Area of stationary object
If package size is reduced, then integration density increases, but EMI shielding becomes more challenging
Solution Approach 1:
The patent implements nested EMI shielding structures where conductive shielding layers are integrated within the substrate layers themselves. The shielding structures are nested within the vertical stack of substrate layers, creating compact EMI barriers that fit within the reduced package footprint while maintaining effective electromagnetic interference protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a reduced microelectronic package size, improved thermal performance, and efficient EMI shielding, allowing for increased functionality integration on a single die with fewer packaging layers, thus addressing the limitations of legacy packages.
Implementation Method 1
insufficient thermal paths
Implementation Method 2
mold interconnects for EMI shielding
Data Source
AI summary
Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.