Substrate Integrated Posts and Heat Spreader Customization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging solutions face challenges with thermal management in multi-chip packages due to issues like TIM degradation, thermal cross-talk, and increased complexity and cost, particularly with traditional lid designs that require custom features and materials, leading to higher thermal resistance and manufacturing complexities.
Innovation Solution
The implementation of substrate integrated posts and customized integrated heat spreaders using high throughput additive manufacturing, along with highly conductive layers deposited via cold spray, allows for a universal lid design that can be shared across multiple packages, reducing thermomechanical stresses and enabling the use of solder thermal interface materials without the need for wafer-level backside metallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If traditional custom lid designs are used for each package, then thermal management can be optimized for specific packages, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent implements a universal lid design that can be used across multiple different packages instead of creating custom lids for each package. This universal lid incorporates standardized features that work with various die configurations, thereby reducing manufacturing complexity while maintaining adequate thermal management performance across different applications.
Solution Approach 2:
The patent uses additive manufacturing to vary geometric parameters of the lid (such as leg positions, heights, and thicknesses) without changing the fundamental lid design. This allows optimization for specific thermal requirements while using the same manufacturing process and base design, reducing overall complexity.
2Temperature
If solder thermal interface material is used to reduce thermal resistance, then thermal performance improves, but the process complexity increases due to required wafer-level backside metallization
Solution Approach 1:
The patent extracts the metallization requirement from the wafer-level fabrication process and relocates it to the package level. By implementing metallization on the substrate or package substrate rather than requiring wafer-level backside metallization, the patent enables solder TIM usage without the complex backend fabrication steps.
Solution Approach 2:
The patent introduces an intermediary metallized layer on the substrate that serves as the bonding surface for solder TIM. This intermediary layer eliminates the need for direct wafer-level metallization while still enabling the use of high-performance solder thermal interface materials.
3Ease of manufacture
If polymer thermal interface material is used, then the process is simpler, but thermal resistance is higher compared to solder TIM
Solution Approach 1:
The patent employs composite thermal interface solutions that combine the advantages of both polymer and solder TIMs. This may involve using solder TIM in critical high-heat areas while using polymer TIM in less critical areas, or using a hybrid material that provides both the thermal conductivity of solder and the ease of application of polymer TIM.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances thermal management by reducing thermal resistance, improving reliability, and simplifying the manufacturing process, while allowing for cost-effective customization and flexibility in material selection and patterning, thus addressing the limitations of traditional packaging methods.
Implementation Method 1
highly conductive layers deposited via cold spray
Data Source
AI summary
A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.