Semiconductor Wiring Substrate Layout for Crosstalk Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor wiring substrates fail to meet the increasing demands for high-bandwidth memory data transfer rates and signal eye width due to inefficiencies in signal trace and ground trace arrangements, leading to suboptimal signal quality and crosstalk.
Innovation Solution
A semiconductor wiring substrate design featuring alternating signal and ground traces with specific spacing and dielectric layer thickness ratios, which reduces electromagnetic wave coupling and crosstalk, enhancing signal quality by ensuring uniform impedance distribution across circuit layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal traces and ground traces are arranged in conventional patterns, then manufacturing is simpler, but signal quality deteriorates due to increased crosstalk and electromagnetic coupling
Solution Approach 1:
The patent applies asymmetry by implementing a non-uniform spacing arrangement where signal traces are spaced at different distances from adjacent ground traces. Specifically, first signal traces are spaced at a first spacing from first ground traces, while second signal traces are spaced at a second spacing from second ground traces, where the first and second spacings are different. This asymmetric configuration optimizes electromagnetic field distribution to reduce crosstalk and improve signal quality without requiring complete redesign of the entire trace pattern.
Solution Approach 2:
The patent implements local quality by applying different spacing configurations to different regions of the circuit layer. Certain signal traces receive enhanced ground trace spacing in high-crosstalk regions, while other areas maintain standard spacing. This localized optimization allows critical signal paths to receive special attention for crosstalk reduction without unnecessarily complicating the entire substrate design.
2Productivity
If data transfer rate is increased to meet high-bandwidth requirements, then productivity improves, but signal integrity worsens due to narrower signal eye width
Solution Approach 1:
The patent applies parameter changes by systematically adjusting the spacing parameters between signal traces and ground traces. By varying the spacing distances (first spacing and second spacing) as key parameters, the electromagnetic coupling between adjacent traces is reduced, thereby maintaining signal eye width even at higher data transfer rates. This parameter optimization enables the system to achieve 8.4 Gbps data transfer while preserving signal integrity.
3Reliability
If uniform spacing is used between signal traces and ground traces, then manufacturing precision is easier to control, but electromagnetic coupling increases leading to worse signal quality
Solution Approach 1:
The patent implements asymmetry by deliberately using non-uniform spacing between signal traces and ground traces. The first spacing and second spacing are intentionally made different to optimize electromagnetic field distribution. This asymmetric approach reduces electromagnetic coupling and improves signal quality, while the spacing values are still controlled within manufacturing tolerances to remain practical for fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves signal integrity and data transfer rates by increasing signal eye width by 32% and achieving higher data transfer rates, such as 8.4 Gbps, compared to conventional designs.
Implementation Method 1
reduces electromagnetic wave coupling and crosstalk
Implementation Method 2
ensuring uniform impedance distribution across circuit layers
Data Source
AI summary
A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.