Substrate Layout With Underfill Barriers for Higher NAND Package Capacity
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Solution Overview
Problem
Conventional SSD manufacturing methods result in a significant 'keep out zone' (KOZ) due to the dispensing of underfill material, which limits substrate real estate and hampers component placement as NAND footprint sizes increase.
Innovation Solution
A wire-bonding finger strip is positioned between the flip-chip and NAND die stack, and a solder mask is placed adjacent to the flip-chip on non-adjacent sides to inhibit the flow of underfill material, thereby reducing the KOZ and optimizing substrate layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If underfill material is dispensed adjacent to the flip-chip to protect the connection, then reliability of the flip-chip to substrate connection is improved, but the keep out zone (KOZ) area increases, reducing substrate real estate available for component placement
Solution Approach 1:
The substrate is divided into distinct functional zones: a first substrate area for the flip-chip assembly with underfill containment, and a second substrate area for NAND die placement. This segmentation allows the underfill to be confined to its necessary functional area while freeing up substrate real estate for additional components.
Solution Approach 2:
A barrier structure (such as a solder mask layer or physical wall) is introduced as an intermediary element between the underfill material and the NAND die placement area. This barrier contains the underfill within the keep out zone while allowing the substrate space beyond the barrier to be used for component placement.
2Quantity of substance
If NAND footprint sizes are increased to improve storage capacity, then product capacity is improved, but the substrate real estate available for other components is reduced
Solution Approach 1:
The substrate layout is segmented into dedicated zones: one zone for high-capacity NAND die with larger footprints, and another zone for the flip-chip controller. The barrier structure defines clear boundaries that allow large NAND die to be placed efficiently without encroaching on the controller area, maximizing overall substrate utilization.
3Area of stationary object
If the keep out zone is reduced to increase package capacity, then substrate space utilization is improved, but underfill material may flow beyond the flip-chip footprint, compromising connection protection
Solution Approach 1:
A barrier structure (solder mask layer or physical containment wall) serves as an intermediary that allows the underfill to flow freely within the keep out zone to protect the flip-chip connection, while simultaneously preventing it from flowing beyond the designated zone. This enables reduced KOZ dimensions without compromising connection protection.
Data Source
AI summary
A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.