Substrate-less Integrated Electronic Module for High-Density Semiconductor Packages
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Solution Overview
Problem
The challenge is to increase the integration density and reduce the footprint of semiconductor packages by efficiently arranging electronic elements of different sizes and types, particularly capacitors, in a compact and high-capacity design, as existing solutions like Silicon-based capacitors and multi-layered ceramic capacitors require large footprints due to their low capacitance per unit area and varying shapes.
Innovation Solution
The solution involves an integrated electronic element module with a substrate-less design, where electronic elements like capacitors, resistors, and ICs are encapsulated in a molding compound with exposed electrical connectors on a planar surface, allowing for direct connection to a redistribution layer (RDL) without a substrate, enabling tighter packing and eliminating the need for elongated connecting structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitors (Si-based or MLCCs) are used in memory packages, then capacitance function is provided, but footprint area increases due to low capacitance per unit area and varying shapes
Solution Approach 1:
The patent merges multiple electronic elements (capacitors, resistors, inductors, ICs) into a single integrated module with a common molding compound and shared electrical connection structure. This consolidation eliminates the need for separate substrate mounting areas for each component, achieving high integration density while providing sufficient total capacitance (up to 25 μF) through multiple capacitor elements working together.
Solution Approach 2:
The patent transitions from planar 2D arrangement of discrete components on a substrate to a 3D integrated module where elements are vertically stacked and interconnected. The electrical connectors extend through the molding compound to provide direct vertical connections to the RDL, eliminating elongated horizontal connecting structures and reducing the footprint area significantly.
2Reliability
If discrete electronic elements are mounted on a substrate using SMT process, then electrical connections are established, but device complexity and footprint increase due to substrate and connecting structures
Solution Approach 1:
The patent extracts and eliminates the substrate from the traditional SMT mounting structure. Electronic elements are directly integrated into the molding compound with electrical connectors that extend directly to the RDL, removing the intermediate substrate layer and its associated complexity while maintaining reliable electrical connections.
Solution Approach 2:
The molding compound serves multiple functions simultaneously: it provides structural encapsulation for electronic elements, acts as an insulating medium, and integrates electrical connection structures. This multi-functionality eliminates the need for separate substrate and connection structures, reducing overall device complexity.
3Productivity
If high arrangement density of semiconductor devices and electronic elements is achieved, then package capacity increases, but manufacturing difficulty increases due to tight spacing and different element types
Solution Approach 1:
The patent segments the integrated module into distinct functional regions within the molding compound, with electronic elements arranged in optimized patterns. The electrical connectors are segmented into individual traces that can be independently routed to different elements, allowing tight spacing while maintaining manufacturability through systematic layout design.
Data Source
AI summary
A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.