Silicon Substrate-less Interposer for Multi-chip Packaging
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Solution Overview
Problem
The complexity, cost, and design challenges associated with through-silicon vias (TSVs) in traditional chip packaging technologies, which increase manufacturing time and complexity, capacitive loading issues, and handling difficulties.
Innovation Solution
A silicon substrate-less interposer with metallization layers and microbumps is used to connect integrated circuit dies, eliminating the need for TSVs and allowing for secure stacking of dies to reduce manufacturing complexity and cost, while providing secure communication through metallization layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to electrically connect dies to the board, then electrical connectivity is achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent removes the TSV structure from the chip package by using a substrate-less interposer design. The interposer provides electrical connectivity through alternative means (metallization layers on a carrier substrate) rather than through-silicon vias, thereby eliminating the manufacturing complexity and cost associated with TSV formation while maintaining the essential electrical connection function
Solution Approach 2:
The substrate-less interposer acts as an intermediary component between the dies and the final mounting substrate. It provides the necessary electrical interconnection and mechanical support without requiring TSVs, thus mediating the connection in a way that avoids the harmful complexity of TSV manufacturing processes
2Reliability
If TSVs are formed through the silicon substrate, then electrical connection is established, but fabrication time and cost increase
Solution Approach 1:
The patent extracts the time-consuming TSV formation process from the manufacturing sequence by adopting a substrate-less interposer architecture. The electrical connections are established through metallization layers deposited on the interposer substrate, which can be done more quickly and efficiently than forming TSVs through silicon, thereby reducing overall fabrication time while maintaining reliable electrical connection
3Reliability
If TSVs are used for die mounting, then electrical connectivity is achieved, but design complexity increases
Solution Approach 1:
The patent removes TSV-related design complexity by eliminating the TSV structure entirely. The substrate-less interposer provides electrical connectivity through conventional metallization and routing techniques, which are simpler to design and implement compared to TSV-based solutions, thereby reducing design complexity while maintaining reliable electrical connection
4Reliability
If TSVs are implemented in chip packaging, then through-substrate connection is achieved, but handling difficulty increases
Solution Approach 1:
The patent extracts the handling difficulties associated with TSVs by removing the TSV structure from the design. The substrate-less interposer with its planar metallization layers provides robust mechanical and electrical connection that is easier to handle and assemble compared to fragile TSV-based structures, thereby improving ease of operation while maintaining through-substrate connection capability
Data Source
AI summary
Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.