Substrate-less Interposer Using Segmented Metallization
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Solution Overview
Problem
The complex fabrication process of interposer substrate layers with through-silicon-vias in silicon stacked interconnect technology (SSIT) products is undesirable for certain applications due to the multiple steps involved, such as forming TSVs, backside thinning, and chemical vapor deposition, which complicates the manufacturing process.
Innovation Solution
A substrate-less interposer technology is introduced, featuring a plurality of metallization layers with metal segments separated by dielectric material, a dielectric layer with openings for contact, a passivation layer, and an underbump metal layer, which eliminates the need for an interposer substrate layer with TSVs, allowing for simpler fabrication while maintaining high-density interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an interposer substrate layer with through-silicon-vias is used, then high-density interconnections are achieved, but the fabrication process complexity increases
Solution Approach 1:
The patent extracts and removes the interposer substrate layer from the traditional SSIT structure, retaining only the essential metallization layers and dielectric materials needed for interconnection. This eliminates the complex TSV formation process while maintaining the high-density interconnection capability through direct metallization patterns on the package substrate.
Solution Approach 2:
The interposer structure is segmented into discrete metallization layers separated by dielectric materials, allowing each layer to be formed independently through standard PCB fabrication processes. This segmentation eliminates the need for through-silicon-via formation while maintaining the layered interconnection architecture.
2Reliability
If multiple fabrication steps including TSV formation, backside thinning, and CVD are performed, then through-silicon-via interposer is created, but the manufacturing time and cost increase
Solution Approach 1:
The patent extracts and eliminates the time-consuming steps of TSV formation, backside thinning, and CVD processing by removing the substrate layer entirely. The essential interposer functionality is achieved through simplified metallization layers formed on the package substrate using standard PCB techniques.
Solution Approach 2:
The patent replaces the permanent, complex TSV-based interposer substrate with a simpler, disposable-like metallization layer structure that can be formed and discarded more easily. This approach uses standard PCB metallization processes instead of specialized semiconductor fabrication steps.
3Reliability
If an interposer substrate layer with TSVs is fabricated, then connectivity between IC dies and package substrate is provided, but the thin wafer handling complexity increases
Solution Approach 1:
The patent extracts and removes the thin interposer substrate layer that requires complex handling. Connectivity is maintained through metallization layers formed directly on the package substrate, eliminating the need for thin wafer manipulation and handling procedures.
Data Source
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AI summary
A substrate-less interposer (201) for a stacked silicon interconnect technology (SSIT) product (200), includes: a plurality of metallization layers (109), at least a bottom most layer of the metallization layers comprising a plurality of metal segments (111), wherein each of the plurality of metal segments (111) is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers (109), and the metal segments (111) are separated by dielectric material (113) in the bottom most layer; and a dielectric layer (203) formed on the bottom surface of the bottom most layer, wherein the dielectric layer (203) includes one or more openings for providing contact to at least some of the plurality of metal segments (111) in the bottom most layer.