3D Memory Substrate Level Difference Lithography Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In three-dimensional memory devices, the difference in level between the cell array and peripheral circuit regions affects the accuracy of patterns formed by lithography, leading to potential distortions and inaccuracies in semiconductor manufacturing.
Innovation Solution
A semiconductor device design featuring a substrate with a first stacked portion, a semiconductor body, a charge storage portion, a circuit portion, and a second stacked portion, where the second stacked portion includes alternating layers to reduce stress and maintain planarity, thereby improving lithography accuracy and reducing distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a three-dimensional memory device is manufactured with a cell array and peripheral circuit regions at different levels, then the device functionality is achieved, but the lithography pattern accuracy deteriorates due to level differences causing distortions
Solution Approach 1:
The patent introduces an intermediate terrace region between the cell array and peripheral circuit regions, creating a stepped structure that transitions between different elevation levels. This dimensional approach allows the substrate to accommodate both high-level cell arrays and low-level peripheral circuits while maintaining a gradual transition zone that minimizes lithography distortions caused by abrupt level changes.
Solution Approach 2:
The substrate surface is segmented into distinct regions: a first region for cell arrays, a second terrace region with intermediate level, and a third region for peripheral circuits. This segmentation creates discrete elevation zones that manage stress distribution and reduce the impact of level differences on lithography accuracy in each specific region.
2Stability of the object's composition
If the substrate has significant level differences between cell array and peripheral circuit regions, then device functionality is maintained, but stress concentration increases causing substrate distortion
Solution Approach 1:
By creating a stepped substrate structure with intermediate terrace regions, the patent distributes stress across multiple elevation levels rather than concentrating it at a single abrupt transition. The intermediate regions act as stress buffers that gradually transition between high and low areas, maintaining overall substrate planarity while accommodating necessary level differences for device functionality.
Data Source
AI summary
According to one embodiment, the circuit portion includes a transistor provided at a region separated from the first stacked portion in the substrate. The second stacked portion is provided above the circuit portion. The second stacked portion includes a plurality of first layers and a plurality of second layers. The first layers and the second layers include a first layer and a second layer stacked alternately. An insulating layer is provided above the circuit portion and provided above the substrate between the first stacked portion and the second stacked portion. A height of an uppermost first layer of the second stacked portion from a surface of the substrate is substantially equal to a height of an uppermost electrode layer of the first stacked portion from the surface of the substrate, or is higher than the height of the uppermost electrode layer.