Substrate Structure Reducing Thermal Stress via Localized Insulation
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Solution Overview
Problem
Conventional 3D chip stacking substrates face challenges in thermal stress management due to large contact surfaces and coefficient of thermal expansion differences between the carrier and insulating layers, leading to warpage and poor stress reliability of conductive elements.
Innovation Solution
A substrate structure with a reduced wiring area, featuring a first insulating layer formed only on junction portions and a second insulating layer with vias exposing the wiring layer, which reduces the contact area and coefficient of thermal expansion differences, thereby enhancing stress reliability and preventing warpage during thermal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the first insulating layer is formed on the entire surface of the carrier, then the electrical insulation is improved, but the contact surface area increases leading to larger thermal stress and warpage
Solution Approach 1:
The first insulating layer is formed only on the wiring area of the carrier surface, not the entire surface. This localized approach provides sufficient electrical insulation where needed (on the wiring area) while minimizing the contact surface area between the insulating layer and carrier, thereby reducing thermal stress and preventing substrate warpage.
2Stability of the object's composition
If the contact surface between carrier and insulating layer is reduced, then thermal stress is released, but the electrical connection reliability may be compromised
Solution Approach 1:
The insulating layer is precisely positioned only on the wiring area where electrical insulation is required, maintaining electrical connection reliability in functional areas while minimizing overall contact surface area to enable thermal stress release.
Solution Approach 2:
The carrier surface is divided into functional areas (wiring area requiring insulating layer) and non-functional areas (where no insulating layer is formed). This segmentation allows the insulating layer to cover only the necessary portion, balancing electrical insulation needs with thermal stress management.
3Stability of the object's composition
If the coefficient of thermal expansion difference between carrier and insulating layer is reduced, then thermal stress is minimized, but material selection becomes more restricted
Solution Approach 1:
Instead of focusing on finding materials with matched thermal expansion coefficients, the invention changes the approach by minimizing the contact surface area between materials with different thermal expansion properties. This parameter change (from material property matching to geometric configuration) reduces thermal stress while maintaining material selection flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The substrate structure efficiently releases thermal stress, minimizing warpage and improving the reliability of conductive elements by reducing the contact area and thermal expansion differences between the carrier and insulating layers.
Implementation Method 1
the difference of coefficient of thermal expansion (CTE) between the two layers is also very large. Therefore, during the thermal cycle it is difficult for the conventional substrate structure 1 to release thermal stress, and warpage of the conventional substrate structure 1 will be caused easily
Data Source
AI summary
A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.