Substrate Structuring with Micro-Blasting for High-Aspect-Ratio Features
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Solution Overview
Problem
The increasing demand for miniaturized electronic devices and complex integrated circuits poses challenges in substrate structuring, particularly with organic package substrates, which are impractical due to limitations in material structuring resolution and high costs associated with silicon interposer fabrication, such as high-aspect-ratio silicon via etching and chemical mechanical planarization.
Innovation Solution
A method involving bonding a substrate to a carrier plate with adhesive layers, patterning a resist layer using electromagnetic radiation, and micro-blasting with powder particles to form structured patterns, followed by an etch process to remove debris and smooth surfaces, allowing for efficient substrate structuring with reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic package substrates are used for fabrication, then ease of forming features and connections is improved, but material structuring resolution becomes insufficient for device scaling
Solution Approach 1:
The patent replaces conventional mechanical and chemical etching processes with micro-blasting technology that uses pressurized gas streams to propel abrasive particles at the substrate surface. This substitution enables precise material removal with superior resolution for through-substrate vias and complex 3D structures, overcoming the resolution limitations of organic package substrates while maintaining ease of feature formation.
2Reliability
If silicon interposers are used for 2.5D and 3D integrated circuits, then high-bandwidth density and lower-power communication are achieved, but manufacturing costs increase due to high-aspect-ratio via etching and chemical mechanical planarization
Solution Approach 1:
The patent replaces complex chemical mechanical planarization (CMP) processes with micro-blasting technology that inherently produces planar surfaces during material removal. This eliminates the need for separate CMP steps, reducing manufacturing process complexity while maintaining the ability to form high-aspect-ratio vias and complex 3D interconnect structures required for high-bandwidth density applications.
Solution Approach 2:
The patent changes the fundamental processing parameters by using controllable pressurized gas streams with adjustable abrasive particle velocity and distribution. This allows precise control over material removal rates and via aspect ratios, enabling cost-effective fabrication of high-aspect-ratio structures without requiring multiple sequential processing steps.
3Manufacturing precision
If conventional etching processes are used for high-aspect-ratio silicon via formation, then via penetration is achieved, but manufacturing costs are imposed by chemical mechanical planarization and BEOL interconnection
Solution Approach 1:
The patent merges multiple separate manufacturing steps into a single micro-blasting operation. The process simultaneously achieves via formation, surface planarization, and debris removal in one step, eliminating the need for sequential chemical etching followed by chemical mechanical planarization. This consolidation reduces process steps while maintaining via formation precision for high-aspect-ratio structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of high aspect ratio features on glass and silicon substrates with lower costs, providing an economical alternative to silicon interposers for advanced integrated circuit packaging.
Implementation Method 1
patterning the resist layer with electromagnetic radiation
Implementation Method 2
propelling powder particles under high pressure towards the substrate to dislodge and remove material from the substrate
Implementation Method 3
exposing the substrate to an etch process to remove debris from the structured patterns and smoothen one or more surfaces thereof
Data Source
AI summary
The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.