Substrate Noise Aware Floorplanning for Mixed-Signal ICs
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Solution Overview
Problem
In integrated circuit design, especially for mixed-signal SOCs, existing methods lack effective early-stage substrate noise estimation and management, leading to inadequate handling of noise coupling between digital and analog components, which degrades analog performance due to uncontrolled substrate noise propagation.
Innovation Solution
A method is developed to create a substrate noise-aware floorplan by generating digital noise models and simulating noise propagation, allowing for the adjustment of circuit block positions to meet noise constraints, using noise observation ports and guard rings to mitigate substrate noise impact on sensitive analog circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If digital and analog blocks are physically separated on the substrate, then substrate noise coupling between digital and analog circuits is reduced, but the chip area increases and routing complexity increases
Solution Approach 1:
The patent applies local quality by creating distinct floorplanning regions with different noise characteristics - digital regions with high switching activity are separated from analog regions with low noise tolerance. The floorplanning tool assigns specific locations to digital and analog blocks based on their noise generation and sensitivity characteristics, ensuring that noise-sensitive analog blocks are placed in regions with lower substrate noise while digital blocks are placed in regions that can tolerate or shield against noise.
2Speed
If digital switching activity is increased to improve processing speed, then substrate noise generation increases, but analog circuit performance degrades
Solution Approach 1:
The patent applies preliminary action by performing substrate noise analysis and floorplanning optimization before final circuit placement and manufacturing. The floorplanning tool uses estimated substrate noise models to predict noise levels at different locations and adjusts the placement of analog and digital blocks accordingly, preventing noise issues before they occur in the final design rather than attempting to fix them after fabrication.
Solution Approach 2:
The patent implements feedback by using substrate noise estimation models that analyze the placement configuration and provide noise level information back to the floorplanning tool. This feedback loop allows the tool to iteratively optimize the placement of digital and analog blocks, moving noise-sensitive blocks away from high-noise areas or adjusting the overall layout to minimize coupling, thereby achieving better noise immunity while maintaining performance.
3Loss of time
If substrate noise analysis is performed early in the design flow, then noise issues can be addressed during floorplanning, but accurate noise estimation requires detailed circuit information that is not yet available
Solution Approach 1:
The patent applies this principle by using simplified, approximate noise models during early floorplanning stages rather than requiring detailed, computationally expensive simulations. The floorplanning tool uses estimated noise models that provide sufficient accuracy for layout optimization without requiring complete circuit netlists or detailed switching waveforms. These approximate models are 'good enough' for the floorplanning stage, and more accurate analysis can be performed later if needed.
Solution Approach 2:
The patent applies parameter changes by adjusting the level of detail and accuracy of noise analysis based on the design stage. During floorplanning, the tool uses coarser-grained noise estimation with fewer parameters, accepting lower precision in exchange for earlier timing. As the design progresses to later stages with more detailed information available, the noise analysis can be refined with more accurate parameters and models, achieving a balance between timing and accuracy at each stage.
Data Source
AI summary
A methodology is provided to perform noise analysis in the implementation stage of the design of an integrated circuit, and based upon analysis results, a floorplan may be adjusted or guard rings may be inserted to reduce the impact of digital switching noise upon noise sensitive circuits.