Semiconductor Substrate Opening Layout for Uniform Display Transistors
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Solution Overview
Problem
Existing semiconductor substrates for display devices face challenges in achieving uniform characteristics due to non-uniformity in the manufacturing process, particularly in the formation of signal lines and connection electrodes, which can lead to variations in transistor characteristics and overall substrate performance.
Innovation Solution
The semiconductor substrate design includes a scanning line, oxide semiconductor layers, insulating layers with specific openings, and a signal line that intersects the scanning line, with the signal line and connection electrode connected through these openings, ensuring that the channel forming regions are protected during the patterning process, thereby reducing non-uniformity and maintaining uniform characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the signal line and connection electrode are formed using conventional patterning processes, then the manufacturing process is simple, but non-uniformity occurs in the semiconductor substrate leading to variations in transistor characteristics
Solution Approach 1:
The insulating layer is divided into multiple segments (first insulating layer, second insulating layer, third insulating layer) with different functions. The first insulating layer covers the semiconductor layer, the second insulating layer contains openings for signal line formation, and the third insulating layer provides additional coverage. This segmentation allows each layer to be optimized for its specific function, improving overall manufacturing precision while managing complexity through functional division.
Solution Approach 2:
The first insulating layer is formed and patterned with openings before the signal line and connection electrode are formed. This preliminary action protects the channel forming regions of the semiconductor layer during subsequent patterning processes, preventing non-uniformity from propagating to the transistor characteristics. The protective structure is prepared in advance to ensure uniformity is maintained throughout the manufacturing process.
2Manufacturing precision
If the channel forming regions are exposed during signal line formation, then the patterning process is straightforward, but non-uniformity occurs in the semiconductor substrate
Solution Approach 1:
The first insulating layer acts as an intermediary protective layer between the channel forming regions of the semiconductor layer and the signal line formation process. This intermediary structure shields the sensitive channel regions during patterning, preventing non-uniformity from occurring. The mediator approach allows the patterning process to proceed while maintaining protection of critical regions, balancing manufacturing ease with precision.
3Reliability
If conventional transistor structures are used, then the device structure is simple, but transistor characteristics vary due to manufacturing non-uniformity
Solution Approach 1:
Different insulating layers are applied with specific local qualities and functions. The first insulating layer provides protection to the channel forming regions, the second insulating layer facilitates signal line formation with appropriate openings, and the third insulating layer provides additional coverage. This local quality approach ensures that each region of the device has the specific properties needed for its function, improving transistor performance consistency while managing overall complexity through targeted functional differentiation.
Data Source
AI summary
According to one embodiment, a semiconductor substrate, comprising, a first semiconductor layer and a second semiconductor layer that overlap a scanning line, an insulating layer that covers the first semiconductor layer and the second semiconductor layer, and a signal line, wherein the insulating layer has a first opening including a pair of long sides and a pair of short sides, the long sides of the first opening are parallel to the second direction, and the short sides of the first opening are parallel to the first direction, and the signal line is connected to the first semiconductor layer and the second semiconductor layer via the first opening.


