Electronic Component Built-in Substrate Oxygen Plasma Etching
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Solution Overview
Problem
Existing methods for manufacturing electronic component built-in substrates are costly due to the need for complex equipment and processes, particularly when forming via holes in insulating layers using lasers or polishing copper posts, which can damage heat-sensitive semiconductor chips and increase manufacturing costs.
Innovation Solution
A method involving a metal protection layer on the semiconductor chip, which is embedded in an insulating layer and then exposed using oxygen plasma etching, eliminating the need for laser via formation and reducing equipment investment by simplifying the manufacturing process and avoiding thermal damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser processing is used to form via holes in the insulating layer, then via holes can be formed precisely, but a laser stop layer must be formed on the connection pads requiring complicated steps and wafer process equipment increasing cost
Solution Approach 1:
The patent extracts the metal protection layer from its traditional role as merely a protective coating and repurposes it as a functional wiring layer. By removing the need for laser stop layer formation and via hole drilling, the process complexity is reduced while maintaining precision through the metal layer's inherent patterning capability
Solution Approach 2:
Instead of forming via holes through the insulating layer to reach connection pads (traditional approach), the patent inverts the approach by having the metal protection layer itself serve as the wiring layer that contacts the connection pads directly, eliminating the need for via holes and stop layers
2Reliability
If copper posts are formed on the wiring substrate and exposed by polishing the insulating layer, then electrical connection is achieved, but expensive polishing equipment is required increasing manufacturing cost
Solution Approach 1:
The patent replaces expensive CMP polishing equipment with conventional, cheaper processing methods. The metal protection layer is processed using standard photolithography and etching techniques that are already present in most manufacturing lines, eliminating the need for costly polishing equipment while maintaining reliable electrical connections
Solution Approach 2:
The patent uses the metal protection layer as a template or copy of the desired wiring pattern. By forming the metal layer conformally and then selectively removing portions, the wiring pattern is obtained without requiring complex polishing processes, reducing equipment costs while maintaining connection reliability
3Reliability
If the insulating layer is processed to expose the connection pad, then electrical connection is enabled, but heat-sensitive semiconductor chips may be damaged by thermal processes
Solution Approach 1:
The metal protection layer is formed and patterned on the semiconductor chip before mounting, serving as a pre-prepared wiring layer. This preliminary action enables electrical connections to be established through the metal layer itself rather than through subsequent thermal via hole formation processes that could damage the chip
Solution Approach 2:
The metal protection layer acts as an intermediary between the connection pads and the external wiring. It provides a thermally stable, electrically conductive path that enables connections without requiring additional thermal processing steps that could damage the heat-sensitive semiconductor chip
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, improves electrical characteristics by shortening wiring lengths, enhances reliability by avoiding thermal damage, and allows for the use of heat-sensitive semiconductor chips without the need for expensive polishing equipment.
Implementation Method 1
processing the insulating layer in a thickness direction to leave the insulating layer in a side of the electronic component and to expose the metal protection layer of the electronic component
Data Source
AI summary
A method of manufacturing an electronic component built-in substrate, includes the steps of mounting a chip-like electronic component having a connection pad and a metal protection layer formed on a whole of one surface to cover the connection pad, on a wiring substrate to direct the connection pad upward; embedding the electronic component with the insulating layer; processing the insulating layer in a thickness direction to leave the insulating layer in a side of the electronic component and to expose the metal protection layer of the electronic component; and forming an upper wiring layer having an in-chip wiring part which is connected to the connection pad and contacts an upper surface of the electronic component and is constructed by an underlying metal pattern layer formed by patterning the metal protection layer and a conductive pattern layer formed thereon, and an extended wiring part which is connected to the in-chip wiring part to extend onto the insulating layer and is formed by an identical layer as the conductive pattern layer.