Semiconductor Substrate-on-Substrate Package with Floating Test Electrode
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Solution Overview
Problem
Current semiconductor substrate testing methods are time-consuming and unreliable, particularly due to the challenge of detecting electrical failures at the interface between stacked substrates with different thermal expansion coefficients, which can lead to mechanical stress and failure during normal operation.
Innovation Solution
The implementation of a semiconductor assembly with a high-density array of electrically interconnected substrates, where an electrically conducting layer with perforations serves as a 'floating' test electrode, allowing for rapid and reliable testing by applying a test voltage that detects insulation breakdowns without being connected to the substrate's power supply during normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If package-level testing is performed using traditional socket testing methods, then testing can be conducted to screen failed packages, but the testing process becomes time-consuming and unreliable
Solution Approach 1:
The patent implements preliminary testing actions by integrating test electrodes and test circuits directly into the substrate structure before final packaging. This allows testing to be performed at an earlier stage in the manufacturing process, eliminating the need for time-consuming post-packaging socket testing and improving both reliability and speed of testing.
Solution Approach 2:
The patent introduces test electrodes and test circuits as intermediary elements that facilitate direct electrical contact with the semiconductor devices during testing. These intermediaries enable reliable signal transmission without requiring external socket connections, thereby improving testing reliability while reducing testing time.
2Adaptability or versatility
If semiconductor substrates with different thermal expansion coefficients are stacked together, then device integration is achieved, but mechanical stress and failure occur during normal operation
Solution Approach 1:
The patent applies local quality by creating through-substrate vias and interconnect structures at specific locations where thermal stress concentration occurs. These localized structural modifications compensate for thermal expansion mismatches between different substrate materials, allowing integrated stacking of substrates with different thermal properties while maintaining operational reliability.
Solution Approach 2:
The patent implements beforehand cushioning by designing compliant interconnect structures and stress-compensation features during the manufacturing process. These pre-built structural elements absorb and distribute thermal stresses before they can cause mechanical failure during normal operation, enabling reliable integration of substrates with different thermal expansion coefficients.
3Reliability
If electrical interconnects are made at the substrate interface, then electrical connection between stacked substrates is achieved, but insulation breakdowns are difficult to detect
Solution Approach 1:
The patent implements preliminary action by incorporating test electrodes and diagnostic circuitry directly at the substrate interface during manufacturing. This allows electrical connections to be tested and verified before final assembly, making insulation breakdowns and other failures easily detectable without requiring complex external testing equipment.
Solution Approach 2:
The patent applies self-service by integrating self-test capabilities directly into the electrical interconnect structure. The test circuits can automatically detect insulation breakdowns and connection failures without external intervention, simplifying the detection process and improving reliability verification while maintaining robust electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces testing time, enhances production yield, and improves operational reliability by identifying and preventing mechanical failures caused by thermal expansion mismatches, while maintaining product robustness against single contact failures.
Implementation Method 1
an electrically conducting layer with perforations serves as a 'floating' test electrode, allowing for rapid and reliable testing by applying a test voltage that detects insulation breakdowns
Implementation Method 2
detecting electrical failures at the interface between stacked substrates with different thermal expansion coefficients, which can lead to mechanical stress and failure during normal operation
Data Source
AI summary
A semiconductor assembly includes a first semiconductor substrate having a first main surface and a second main surface and a second semiconductor substrate having a first main surface and a second main surface. The first main surface of the first semiconductor substrate faces the second main surface of the second semiconductor substrate. Further, the semiconductor assembly includes a plurality of first electrodes disposed on the first main surface of the first semiconductor chip and a plurality of second electrodes disposed on the second main surface of the second semiconductor chip, wherein the first electrodes are aligned with and connected by interconnects to the second electrodes. An electrically conducting layer perforated by holes is disposed between and fixed to the first semiconductor substrate and the second semiconductor substrate, wherein the interconnects penetrate the holes. The electrically conducting layer is electrically connected to a function test electrode of the semiconductor assembly.