Substrate Package Side Wettable Flanks for Solder Joint Inspection
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Solution Overview
Problem
The quality of electrical contacts in existing substrate-based package semiconductor devices is not always satisfactory, and the methods to verify their reliability are inadequate.
Innovation Solution
A carrier is used to fabricate non-singulated substrate-based package semiconductor devices with cavities near the package terminals, where the inner walls of these cavities are covered with a conductive body that connects to the terminals, allowing for stronger solder joints and enabling automatic visual inspection post-assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional leadframe based packages are used, then manufacturing is simpler, but parasitic capacitance and inductance are high which degrades RF performance
Solution Approach 1:
The patent changes the fundamental parameters of the package structure by transitioning from leadframe-based design to substrate-based design with organic laminate materials. This enables optimized trace layouts, controlled impedance, and reduced parasitics while maintaining manufacturability through standardized substrate fabrication processes
Solution Approach 2:
The patent employs composite material structures combining organic laminate substrates with metal trace layers and solder balls. This composite approach allows simultaneous achievement of low parasitic electrical characteristics and mechanical robustness required for RF applications
2Reliability
If substrate-based packages with optimized layout are used, then parasitic capacitance and inductance are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming cavities in the substrate before mounting the semiconductor die. This preliminary cavity formation enables subsequent easy application of conductive paste and ensures proper alignment, thereby simplifying the overall manufacturing process while maintaining high electrical contact quality
Solution Approach 2:
The patent segments the substrate into functional regions including cavity areas, die mounting areas, and terminal areas. This segmentation allows independent optimization of each region and simplifies the manufacturing process by enabling modular fabrication steps
3Measurement precision
If visual inspection techniques are used to verify electrical contact quality, then contact quality can be assessed, but the inspection process is manual and time-consuming
Solution Approach 1:
The patent employs color changes or optical contrast differences between the conductive paste and substrate material. This optical contrast enables automatic visual inspection systems to quickly and accurately detect the presence and quality of electrical contacts, transforming manual inspection into an automated high-speed process
Solution Approach 2:
The patent creates a visual copy or representation of the electrical contact quality through optical imaging. This optical copy can be automatically analyzed by inspection systems, enabling rapid assessment of contact quality without manual intervention and significantly improving productivity
Data Source
AI summary
A substrate-based package semiconductor device is provided. The present disclosure further relates to a carrier including a plurality of non-singulated substrate-based package semiconductor devices and to a method of manufacturing the same. In embodiments in accordance with the present disclosure, the lowest insulating layer(s) has/have cavities arranged near and associated with one or more package terminals, and an inner wall of the cavities is covered with a conductive body that connects to the respective associated package terminal. Furthermore, the non-singulated substrate-based package semiconductor devices are separated by a separating region of the substrate, and the cavities are at least partially formed in the separating region.