Substrate Packaging Structure with Conductive Blocks for Low Inductance
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Solution Overview
Problem
Current optical communication link packaging structures face bandwidth limitations due to high inductance and impedance mismatch, particularly affecting high-speed signal transmission beyond 10 Gbps, where gold wire bonding introduces significant bandwidth attenuation and heat dissipation challenges.
Innovation Solution
The proposed substrate packaging structure features a first and second substrate electrically connected with conductive blocks, forming conductive areas on surfaces and sides to create a low-inductance return path through electroplated reference return circuits, improving impedance and increasing bandwidth by providing a three-dimensional reference for signal lines via gold wire bonding and potential tin solder connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold wire bonding is used to connect ceramic substrate and transmission lines, then ease of manufacture and reliability are improved, but bandwidth attenuation increases severely at high frequencies
Solution Approach 1:
The patent extracts the harmful inductance from the connection structure by removing the gold wire bonding process and replacing it with direct soldering connections between substrates, thereby eliminating the primary source of bandwidth attenuation while maintaining manufacturing reliability
Solution Approach 2:
The patent replaces the mechanical wire bonding system with a direct soldering connection system, substituting the flexible wire bonding mechanism with rigid solder joints that have significantly lower inductance and better high-frequency performance
2Ease of manufacture
If DFB lasers with current modulation are used, then cost is reduced and long-distance transmission is enabled, but impedance mismatch occurs due to low internal resistance
Solution Approach 1:
The patent applies local quality by creating a high-impedance region around the laser mounting area through strategic placement of conductive blocks and reference return circuits, locally compensating for the low internal resistance of DFB lasers to achieve impedance matching without changing the laser itself
Solution Approach 2:
The patent changes the electrical parameters of the packaging structure by adjusting the geometry and distribution of conductive blocks and reference return circuits to create high-impedance regions that match the 50-ohm differential impedance requirement for DFB laser operation
3Adaptability or versatility
If conventional two-substrate packaging is used, then device integration is achieved, but inductance increases and bandwidth is limited
Solution Approach 1:
The patent transitions from planar two-dimensional connections to three-dimensional spatial arrangements by forming conductive blocks and reference return circuits in multiple layers and dimensions, creating low-inductance return paths that utilize vertical and lateral spatial relationships to reduce loop area and inductance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances packaging bandwidth beyond 50 GHz and reduces impedance to approximately 51 ohms, enabling ultra-high-speed interconnections at a lower cost by addressing bandwidth and heat dissipation issues.
Implementation Method 1
A first conductive area and a second conductive area are formed on an upper surface and a side surface of the first substrate, respectively. A first reference conductive area is formed below the upper surface of the first substrate.
Data Source
AI summary
A substrate packaging structure includes: a first substrate and a second substrate that are electrically connected; a plurality of conductive blocks arranged on each one of the first substrate and the second substrate, and electrically connected to each other; first and second conductive areas respectively formed on upper and side surfaces of the first substrate; a first reference conductive area formed below the upper surface of the first substrate and electrically connected to the first and second conductive areas; third and fourth conductive areas respectively formed on upper and side surfaces of the second substrate; and a second reference conductive area formed below the upper surface of the second substrate and electrically connected to the third and fourth conductive areas. The first conductive area on the first substrate is electrically connected to the third conductive area on the second substrate.