Substrate Packaging Structure With Printed Through-Hole Interconnects
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Solution Overview
Problem
Existing packaging structures, such as those using through-silicon vias and wire bonding, face issues like residual glue affecting electrical conduction, air gaps, and increased material waste and machining costs due to differences between the center and edge of wafers during hybrid wire bonding.
Innovation Solution
A method involving the formation of a packaging structure by providing substrates with dielectric layers and base materials, connecting them to form a composite structure, thinning the top surface to expose through holes, and forming conductive members within these holes using a printing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias and wire bonding are used in packaging, then electrical conduction is achieved, but residual glue remains that affects electrical conduction
Solution Approach 1:
The patent extracts and removes the harmful residual glue from the bonding interface through cleaning processes between die stacking steps, ensuring that no adhesive remains to interfere with electrical conduction or create air gaps
Solution Approach 2:
The patent applies preliminary cleaning actions before subsequent bonding steps to prevent residual glue from affecting future electrical connections, ensuring each interface is prepared properly before assembly
2Ease of manufacture
If hybrid wire bonding is used, then die bonding is achieved, but air gaps and dish-shaped recesses occur due to differences between center and edge of wafer
Solution Approach 1:
The patent segments the bonding process into multiple steps with intermediate thinning operations, allowing different regions of the wafer to be processed at different rates to compensate for center-edge thickness variations
Solution Approach 2:
The patent employs periodic thinning and bonding cycles, where the structure is thinned, bonded, then thinned again in subsequent steps, allowing progressive correction of flatness issues throughout the assembly process
3Ease of manufacture
If conventional packaging processes are used, then substrates are connected, but material waste and machining costs increase
Solution Approach 1:
The patent merges multiple process steps into integrated operations, such as combining die thinning with bonding preparation and integrating conductive member formation into the stacking sequence, thereby reducing material waste and simplifying manufacturing
Data Source
AI summary
A method for forming a packaging structure is provided. The method includes providing a first substrate and a second substrate. The first substrate includes a first base material and a first dielectric layer on the first base material, and the second substrate includes a second base material and a second dielectric layer on the second base material. The second base material has a first through hole. The first dielectric layer and the second dielectric layer have a first hole and a second hole, respectively. The method further includes connecting the second substrate to the first substrate in such a way that the second dielectric layer is connected to the first dielectric layer to form a first composite structure; thinning the top surface of the first composite structure to expose the first through hole; and forming a first conductive member in the first through hole.