Redistribution Substrate Pad Layout for Reliable Semiconductor Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved structural stability, durability, and reliability, with existing methods often resulting in defects during fabrication and assembly.
Innovation Solution
A semiconductor package design featuring a redistribution substrate with distinct substrate pads of varying heights and widths, where a first substrate pad with a higher height and smaller width is used in conjunction with a second substrate pad, both electrically connected to the semiconductor chip, along with a molding layer to encapsulate the connection terminals, enhancing structural integrity and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate pads of uniform height and width are used, then the fabrication process is simple, but structural stability and reliability are insufficient
Solution Approach 1:
The substrate pad structure is segmented into multiple types (first substrate pads and second substrate pads) with different dimensions. This segmentation allows each pad type to serve specific functional requirements, improving overall structural stability while maintaining manufacturability through standardized fabrication processes.
Solution Approach 2:
Different regions of the substrate pad structure are assigned different qualities (heights and widths) based on local functional requirements. First substrate pads have different dimensions than second substrate pads, allowing optimal local characteristics for specific mounting or electrical connection needs while maintaining overall reliability.
2Reliability
If substrate pads of varying heights and widths are used, then structural stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The invention changes the parameters (height and width) of substrate pads to create different pad types. By systematically varying these parameters within controlled ranges, the design achieves improved durability and reliability while maintaining compatibility with standard manufacturing precision capabilities.
3Reliability
If connection terminals are exposed, then electrical connection is achieved, but defect occurrence increases
Solution Approach 1:
The invention introduces an intermediary protective layer that covers the connection terminals after they are formed. This intermediary structure maintains electrical connectivity while protecting the terminals from environmental factors and mechanical damage, thereby reducing defect occurrence and improving overall connection reliability.
Solution Approach 2:
The protective structure is formed beforehand to shield the connection terminals from potential damage during subsequent fabrication steps and assembly processes. This prior cushioning prevents defects before they can occur, while still allowing electrical connections to be established.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enhances the structural stability and reliability of semiconductor packages by ensuring proper alignment and pressure distribution during chip mounting, reducing the likelihood of defects and improving the overall durability of the package.
Implementation Method 1
performing a plating process in which the seed layer is used as a seed to form a first substrate pad that fills the first opening and a second substrate pad that fills the second opening
Implementation Method 2
performing on the connection members a reflow process to form a first connection terminal that connects the first substrate pad to one of the chip pads and a second connection terminal that connects the second substrate pad to another one of the chip pads
Data Source
AI summary
Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.


