Package Substrate Metal Pad Layer for Reduced Via Size and Bump Pitch

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing integrated circuit (IC) packages face challenges in minimizing inductance in the power distribution network (PDN) due to limitations in reducing the bump pitch of the package substrate, which restricts the density of connections between the deep trench capacitor and the die.

Innovation Solution

The introduction of an additional metal pad layer in the insulating layer of the package substrate's metallization layer reduces the via size by decreasing the aspect ratio, allowing for smaller metal interconnects and a reduced bump pitch, thereby enhancing the power distribution network's performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the bump pitch of the package substrate is reduced to increase connection density between the deep trench capacitor and the die, then the decoupling capacitance and PDN performance are improved, but the via size and aspect ratio constraints prevent further pitch reduction

Engineering Contradiction:
Improveconnection densityVSAvoidvia size
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent introduces an additional metal pad layer within the existing metallization structure, effectively adding a dimensional element to the vertical stack. This allows vias to connect to the new pad layer at a reduced depth, decreasing the via aspect ratio and enabling smaller via sizes that support reduced bump pitch and higher connection density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent modifies the metallization layer parameters by inserting an additional metal pad layer, which changes the vertical distance parameter for via formation. This parameter change reduces the via aspect ratio, allowing for smaller via dimensions and enabling reduced bump pitch to achieve higher connection density

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If the via size is reduced to enable reduced bump pitch, then the connection density is improved, but the via aspect ratio increases making fabrication more difficult

Engineering Contradiction:
Improveconnection densityVSAvoidvia aspect ratio
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By adding an intermediate metal pad layer within the metallization stack, the patent creates an additional connection plane that reduces the vertical distance vias must traverse. This dimensional modification decreases the via aspect ratio, making fabrication easier while enabling reduced bump pitch for higher connection density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If the metal interconnect size is reduced to achieve reduced bump pitch, then the connection density is improved, but the alignment precision required for via-to-interconnect connections increases

Engineering Contradiction:
Improveconnection densityVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The additional metal pad layer acts as an intermediary element between the vias and the metal interconnects. This intermediate pad provides a larger target area for via alignment, reducing the precision requirements for via-to-interconnect alignment while enabling smaller metal interconnect sizes and reduced bump pitch for higher connection density

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250062235A1Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods
Publication Date: 2025.02.20 QUALCOMM INC
  • US20250062235A1 patent drawing
  • US20250062235A1 patent drawing
  • US20250062235A1 patent drawing

AI summary

Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die/bump connections to the package substrate.