Substrate Pad Size Zoning for Flip-Chip Joint Yield

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Solution Overview

Problem

The yield of a flip chip package in bump-on-trace technology is influenced by the size and shape of bumps and pads, requiring careful design to optimize the joint yield and reduce bump shifting.

Innovation Solution

A substrate design with varying pad sizes and trace widths, where the pad size in core and corner areas is larger than in other areas, increasing the bridging window between substrate pads and chip bumps, thereby enhancing joint yield and reducing bump shifting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uniform pad sizes are used across the substrate, then manufacturing is simpler, but joint yield decreases and bump shifting increases

Engineering Contradiction:
Improvejoint yieldVSAvoidpad size variation
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The substrate employs different pad sizes in different regions: larger pads in core and corner areas, and smaller pads in edge areas. This local differentiation optimizes the bridging window for bump alignment in each region, improving joint yield while accommodating the specific geometric constraints of different substrate areas.

Inventive Principle:
Principle #3Local quality

2Reliability

If larger pad sizes are used, then bridging window increases and joint yield improves, but bump shifting control decreases

Engineering Contradiction:
Improvejoint yieldVSAvoidbump shifting control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies different pad sizes locally: larger pads in core/corner areas provide increased bridging window for yield improvement, while smaller pads in edge areas maintain better bump shifting control. This regional differentiation resolves the contradiction by optimizing each area for its specific requirements.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11894332B2Substrate and package structure
Publication Date: 2024.02.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11894332B2 patent drawing
  • US11894332B2 patent drawing
  • US11894332B2 patent drawing

AI summary

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.