Semiconductor Package Substrate Patch Layout for Warpage Relief
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Solution Overview
Problem
The warpage phenomenon in semiconductor packages due to differences in thermal expansion coefficients between components can cause damage to semiconductor chips, especially as trends move towards thinner, more miniature, and lightweight chips.
Innovation Solution
A package substrate with a base layer, upper and lower bump pads, passivation layers, insulating patches, and bump structures, where the insulating patches have patch openings aligned with the passivation layer openings, and an underfill material layer fills the gap between the chip and substrate, with bump structures connecting the chip to the substrate through these openings, and a dam structure surrounding the chip to control the underfill material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If the semiconductor package uses thinner, more miniature, and lightweight chips to reduce weight and size, then the weight and dimensions of the package are reduced, but the chip becomes more susceptible to damage from warpage
Solution Approach 1:
The patent introduces an insulation patch with a specific coefficient of thermal expansion at a particular location (between the chip and upper passivation layer) to locally compensate for warpage. This local quality modification allows the package to maintain overall lightweight design while providing targeted warpage compensation to protect the chip from damage
Solution Approach 2:
The patent utilizes thermal expansion coefficients of different materials to compensate for warpage. The insulation patch is specifically designed with a coefficient of thermal expansion that differs from surrounding materials, allowing it to expand or contract at different rates during thermal cycling, thereby counteracting warpage forces and protecting the chip
2Ease of manufacture
If the package substrate structure is simplified to reduce manufacturing complexity, then ease of manufacture is improved, but warpage control and connection reliability may be compromised
Solution Approach 1:
The package substrate is segmented into distinct functional layers including base layer, upper passivation layer, and insulation patch. This segmentation allows each layer to be optimized for its specific function while maintaining overall manufacturing simplicity. The bump structures are also segmented into multiple layers (first bump structure, second bump structure) that can be formed through standardized processes
Solution Approach 2:
The patent employs composite material structures combining different materials with specific properties - the insulation patch material is selected to have appropriate coefficient of thermal expansion, bump structures use solder materials with specific melting points and bonding characteristics. These composite structures achieve reliable connections and warpage control through material property optimization rather than complex geometric designs
3Device complexity
If bump structures are positioned directly through passivation layer openings without additional insulation, then device complexity is reduced, but non-wet defects may occur due to insufficient gap control
Solution Approach 1:
The insulation patch acts as an intermediary element between the chip and the upper passivation layer. It provides a controlled interface that ensures proper gap formation and alignment for bump structures, preventing non-wet defects by mediating the connection between chip pads and bump structures while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces warpage and prevents non-wet defects, enhancing the reliability of the chip-substrate connection by controlling thermal expansion and filling gaps effectively.
Implementation Method 1
Due to differences in the coefficients of thermal expansion (CTE) between respective components of a semiconductor package, a warpage phenomenon in which a semiconductor package warps may occur
Implementation Method 2
a plurality of bump structures disposed between the plurality of upper bump pads and the semiconductor chip
Data Source
AI summary
A semiconductor package includes a semiconductor chip, and a package substrate including a base layer, a plurality of upper bump pads disposed on the base layer, an upper passivation layer disposed on the base layer, the upper passivation layer including a plurality of first openings, and an insulating patch disposed between an outer region of the semiconductor chip and the upper passivation layer, the insulating patch including a plurality of patch openings, and a plurality of bump structures disposed between the upper bump pads and the semiconductor chip, wherein each of the plurality of bump structures is disposed on a corresponding one of the plurality of upper bump pads through a corresponding one of the plurality of first openings of the upper passivation layer and a corresponding one of the plurality of patch openings of the insulating patch.