Substrate Patterning With Self-Aligned Blocks for Overlay Error Control
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Solution Overview
Problem
In semiconductor device fabrication, the shrinking of feature dimensions leads to increased pattern misalignment issues, particularly at advanced technology nodes, resulting in yield loss due to edge placement errors in metallization patterns with small critical dimensions.
Innovation Solution
The method involves forming self-aligned blocks using selectivities of adjacent columns of different materials and rows of metal oxide resist to restrict the blocks in both horizontal and vertical directions, allowing for the formation of fully self-aligned blocks that reduce edge placement errors in metallization patterns with small critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature dimensions are shrunk to double component density at each technology node, then component density is improved, but pattern misalignment and edge placement errors increase
Solution Approach 1:
The patent segments the patterning process into multiple steps: forming mandrels, depositing spacers, forming metal oxide resist bars, and creating self-aligned blocks. This multi-stage segmentation allows each step to be precisely controlled independently, achieving the required manufacturing precision for sub-15nm features while enabling higher component density through advanced technology nodes
Solution Approach 2:
The patent performs preliminary actions by forming mandrels and spacers before the final patterning step. The mandrels and spacers are prepared in advance with precise dimensions, and the metal oxide resist bars are formed beforehand to serve as alignment references. This preliminary preparation ensures that when the self-aligned blocks are formed, the pattern misalignment is minimized despite the shrunk feature dimensions
2Quantity of substance
If feature dimensions are reduced to near ten nanometers using immersion DUV and EUV lithography, then component density is improved, but overlay requirements become stricter
Solution Approach 1:
The patent implements self-service through self-aligned blocks where the blocks automatically align to the mandrels and spacers without requiring additional overlay steps. The metal oxide resist bars serve as self-aligned references that guide the block formation process. This self-alignment mechanism satisfies the strict overlay requirements for sub-10nm features while maintaining high component density through advanced lithography techniques
Solution Approach 2:
The patent introduces a vertical dimension by forming three-dimensional self-aligned blocks that extend through multiple layers. The blocks are formed with controlled heights and positions in the vertical direction, providing an additional degree of freedom for alignment. This dimensional approach reduces the burden on planar overlay requirements while achieving the necessary precision for near-10nm features
3Manufacturing precision
If self-aligned blocks are formed using multiple materials and orthogonal lines, then edge placement errors are reduced, but process complexity increases
Solution Approach 1:
The patent uses homogeneous material properties within each layer (mandrels, spacers, metal oxide resist, self-aligned blocks) to ensure consistent etching and deposition behavior. The orthogonal lines are formed with uniform dimensions and spacing, creating a regular pattern that simplifies the self-alignment process. This homogeneity reduces edge placement errors while keeping the process manageable despite the multiple materials involved
Data Source
AI summary
A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.