Semiconductor Substrate Pillars Curved Base Coplanarity
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Solution Overview
Problem
Semiconductor package substrates face challenges with non-coplanar pillars due to unpredictable plating parameters, leading to unreliable solder joints, especially in fine pitch and wafer level packaging, where uniform electric current density is critical.
Innovation Solution
The substrate design features pillars with curved or convex base surfaces matching the trace surfaces, ensuring high coplanarity and reliability through a method involving patterned layers, conductive films, and dielectric layers, with conductive vias for electrical connectivity, and a process that includes forming and removing layers to achieve precise pillar formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electroplating is used to form pillars, then manufacturing efficiency is improved, but manufacturing precision deteriorates due to unpredictable plating parameters causing non-coplanar pillar surfaces
Solution Approach 1:
The patent applies preliminary action by forming a planarized dielectric layer over the electroplated pillars before subsequent processing. This pre-leveling step compensates for the non-coplanar surfaces created by electroplating, ensuring that the final pillar tops are coplanar without requiring perfect plating control. The dielectric layer is deposited to fill in the height variations and is then planarized through CMP or etch-back processes.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the electroplated pillars and the subsequent solder bump formation process. This intermediate layer acts as a buffer that masks the surface irregularities of the pillars and provides a uniform surface for subsequent processing, thereby decoupling the pillar formation quality from the final coplanarity requirement.
2Manufacturing precision
If leveling agents, wetting agents, or brighteners are added to the plating bath to improve surface quality, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent extracts the surface leveling function from the plating bath chemistry and relocates it to a separate dielectric layer deposition and planarization process. By removing the requirement for complex plating bath additives, the system simplifies the plating process while achieving the same coplanarity goal through a different mechanism - depositing a planarized dielectric layer over the pillars.
Solution Approach 2:
The patent replaces the chemical mechanism (leveling agents in plating bath) with a mechanical/physical mechanism (dielectric layer deposition and planarization). Instead of relying on chemical additives to modify plating behavior, the system uses physical deposition processes to create a uniform surface, substituting chemical complexity with a more controllable physical process.
3Productivity
If fine pitch solder bumps are used to increase connection density, then productivity improves, but reliability deteriorates due to sensitivity to non-coplanar pillar surfaces
Solution Approach 1:
The patent applies preliminary action by creating a planarized surface over the pillars before applying the fine pitch solder bumps. This pre-leveling ensures that even though the pillars themselves may have height variations from electroplating, the surface where solder bumps are placed is uniform, allowing fine pitch bumps to be applied reliably without being affected by underlying pillar non-coplanarity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high coplanarity of pillar surfaces improves the reliability of semiconductor packages by ensuring consistent electrical connections and uniform current distribution, enhancing the stability and performance of micro-scale patterns.
Implementation Method 1
forming a conductive film covering the plurality of first pillar portions of the plurality of pillars and the patterned layer
Implementation Method 2
The pillars may be formed by electroplating
Data Source
AI summary
The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.