Substrate Plate Embossing Layout for Scratch-Free Wafer Holding
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Solution Overview
Problem
The issue of scratch defects on semiconductor substrates occurs due to warpage caused by high temperatures during chemical vapor deposition processes, exacerbated by embossing patterns on substrate plates.
Innovation Solution
A substrate processing apparatus with a central embossing pattern and radially arranged first and second embossing patterns that support the semiconductor substrate, distributing electrostatic attraction force and aligning with thermal expansion to reduce or eliminate scratch defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embossing patterns are provided on the substrate plate to prevent slippage, then substrate holding stability is improved, but scratch defects occur on the semiconductor substrate due to thermal expansion at high temperature
Solution Approach 1:
The embossing patterns are segmented into multiple types (first embossing patterns extending radially outward and second embossing patterns extending in other directions) with different orientations and lengths. This segmentation allows each pattern type to address specific stress directions, preventing substrate slippage while reducing concentrated friction that causes scratches during thermal expansion.
Solution Approach 2:
Different regions of the substrate plate have different embossing pattern configurations. The first embossing patterns are positioned to handle radial thermal expansion forces, while second embossing patterns address other directional stresses. This local differentiation optimizes holding stability in each region while minimizing scratch risks specific to that area's stress profile.
2Reliability
If electrostatic attraction force is used to hold the semiconductor substrate, then substrate fixation is achieved, but scratch defects are exacerbated when the substrate slips at corners of embossing patterns
Solution Approach 1:
The embossing patterns incorporate curved surfaces and rounded corners instead of sharp angular features. This curvature eliminates stress concentration points at pattern corners, preventing substrate slippage initiation while maintaining electrostatic holding effectiveness across the entire substrate surface.
Solution Approach 2:
The embossing patterns are designed to convert the harmful thermal expansion force into a beneficial holding mechanism. By providing patterns that extend in directions matching thermal expansion, the friction generated during expansion actually enhances substrate adhesion to the plate rather than causing slippage and scratches.
3Productivity
If high temperature is applied for chemical vapor deposition, then deposition process is enabled, but substrate warpage increases due to thermal expansion
Solution Approach 1:
The embossing patterns are strategically designed to accommodate and direct thermal expansion. Patterns extending radially outward from the center align with the natural thermal expansion direction, providing controlled friction that manages warpage while maintaining substrate attachment during high-temperature deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The apparatus stabilizes the semiconductor substrate, reducing or eliminating scratch defects by aligning with thermal expansion and distributing electrostatic force, ensuring stable support during high-temperature processes.
Implementation Method 1
the substrate plate having an electrostatic electrode that is configured to hold down the semiconductor substrate using an electrostatic attraction force
Implementation Method 2
the semiconductor substrate held down by the electrostatic attraction force is thermally expanded by the high temperature
Data Source
AI summary
A substrate processing apparatus includes a chamber providing a space where a semiconductor process is performed on a semiconductor substrate, a substrate plate configured to support the semiconductor substrate, the substrate plate having a central region and a peripheral region surrounding the central region, a central embossing pattern on the central region and configured to support a central portion of the semiconductor substrate, a plurality of first embossing patterns radially arranged around the central embossing pattern on the peripheral region, each of the plurality of first embossing patterns extending radially outward from the central embossing pattern with a first length, and a plurality of second embossing patterns respectively provided between the first embossing patterns on the peripheral region, each of the plurality of second embossing patterns extending radially outward from the central embossing pattern with a second length that is less than the first length.