Substrate Recess Plating Layout for Thinner Chip Packages
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Solution Overview
Problem
Semiconductor packages with a stacked structure face challenges in reducing thickness due to increased overall thickness, necessitating innovative methods for forming recesses in substrates to accommodate semiconductor chips while maintaining electrical performance and electromagnetic shielding.
Innovation Solution
A method involving a copper-clad laminate with formed plating patterns, covered by an insulating layer, where the copper-clad layer is selectively removed to create a semiconductor chip receiving recess, allowing for efficient formation of wiring patterns and reducing package thickness without the need for an interposer substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a stacked structure of multiple substrates is used to achieve package-on-package type semiconductor packages, then vertical expansion and higher performance are realized, but the overall thickness increases
Solution Approach 1:
The patent extracts unnecessary material by forming a recess in the lower substrate by removing a portion of the copper-clad layer and plating pattern. This extraction creates space to accommodate semiconductor chips vertically, enabling package-on-package stacking while reducing the overall thickness increase that would otherwise occur with multiple substrates
Solution Approach 2:
The patent implements nesting by placing semiconductor chips inside the recess formed in the lower substrate. This nested structure allows the chips to be embedded within the substrate thickness rather than adding full substrate thickness, enabling vertical stacking while maintaining compact overall dimensions
2Length of stationary object
If a recess is formed in the lower substrate to reduce package thickness, then the thickness is reduced and interposer substrate is omitted, but the wiring patterns and recess formation become more complex
Solution Approach 1:
The patent applies preliminary action by forming the plating pattern on the copper-clad layer before removing portions to create the recess. This sequence ensures that the recess walls have conductive plating layers pre-formed, so that when chips are inserted, electrical connections are already in place, simplifying the overall manufacturing process despite the complex geometry
Solution Approach 2:
The patent merges multiple functions into the recess structure: it serves as both the chip mounting cavity and the electrical connection pathway. The plating pattern on the recess walls provides both structural definition and electrical conductivity, eliminating the need for separate interposer substrates and reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient formation of semiconductor chip receiving recesses and wiring patterns, reducing package thickness and enhancing electrical performance, while maintaining electromagnetic shielding, thus addressing the thickness and performance challenges of stacked semiconductor packages.
Implementation Method 1
forming the semiconductor chip receiving recess by removing a portion of the copper-clad layer, on which the first plating pattern is arranged, and the first plating pattern
Data Source
AI summary
According to an aspect of the disclosure, a method of manufacturing a substrate having a semiconductor chip receiving recess formed therein, includes preparing a copper-clad laminate having, on at least one surface thereof, a copper-clad layer, forming a first plating pattern on one surface of the copper-clad layer so as to correspond to a position at which the semiconductor chip receiving recess is to be formed, forming a second plating pattern on one surface of the first plating pattern and one surface of the copper-clad layer, arranging an insulating layer to cover the first plating pattern and the second plating pattern, and forming the semiconductor chip receiving recess by removing a portion of the copper-clad layer, on which the first plating pattern is arranged, and the first plating pattern.