Connection Substrate Recession for Under-Fill Crack-Resistant Packaging
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Solution Overview
Problem
Semiconductor packages face reliability issues due to stresses that can cause cracks in the under-fill layer during the fabrication of chip-on-wafer (CoW) structures, which affects the integration and interconnect density of multiple dies on a single package.
Innovation Solution
A semiconductor package design that includes a connection substrate with a recession on its lower corner, featuring a base substrate with upper and lower pads connected by through vias, and under-fill layers to prevent cracking and ensure reliable interconnects, along with a heat radiation structure for thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple dies are incorporated side-by-side on a silicon interposer to achieve better interconnect density, then integration density is improved, but the interposer experiences stresses that lead to cracks on the under-fill layer
Solution Approach 1:
The connection substrate is divided into multiple regions including chip regions for mounting semiconductor chips and scribe line regions positioned between adjacent chip regions. This segmentation allows stress to be distributed and released at the scribe line regions, preventing crack propagation through the under-fill layer while maintaining high integration density through multiple dies on the interposer.
Solution Approach 2:
Different regions of the connection substrate are assigned different functions and properties: chip regions are optimized for electrical connection and chip mounting, while scribe line regions are designed as stress relief zones with different structural characteristics. This local differentiation allows the substrate to simultaneously support high integration density and prevent under-fill layer cracking through targeted stress management at critical locations.
2Productivity
If the interposer is used to mount multiple semiconductor chips, then interconnect density is improved, but stresses cause cracks on the under-fill layer
Solution Approach 1:
The scribe line regions act as intermediary stress relief zones positioned between adjacent chip regions on the connection substrate. These regions serve as mediators that absorb and distribute mechanical stresses generated during chip mounting and operation, preventing stress transmission to the under-fill layer while maintaining the high interconnect density enabled by multiple chips on the interposer.
Solution Approach 2:
The connection substrate is pre-designed with scribe line regions and recession features before chip mounting to create built-in stress relief mechanisms. This beforehand cushioning approach prepares the substrate structure in advance to accommodate thermal expansion and mechanical stresses, preventing under-fill layer cracking before it occurs during operation or subsequent processing steps.
Data Source
AI summary
A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.