Embedded Substrate Reinforcement for Semiconductor Package Coplanarity
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Solution Overview
Problem
High performance computing (HPC) semiconductor packages experience warpage due to mismatched coefficients of thermal expansion (CTE) between the interposer, substrate, and stiffener structure, leading to coplanarity issues and potential electrical opens or shorts during the surface mount process, which reduces the robustness and yield of the semiconductor package.
Innovation Solution
Incorporating a reinforcement structure embedded within the substrate to increase its rigidity, maintaining coplanarity with the circuit board and reducing warpage, by forming a substrate with a bottom and top layer of electrically-conductive traces and a binding material layer that includes the reinforcement structure, which is configured to improve the semiconductor package's rigidity and prevent unacceptable warpage during the surface mount process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor package uses mismatched CTE materials (interposer, substrate, stiffener) to achieve functional requirements, then the electrical connectivity and signal transmission are improved, but the package experiences warpage and coplanarity issues during surface mount process
Solution Approach 1:
The patent changes the physical parameters of the substrate by incorporating a reinforcement structure with different mechanical properties (higher rigidity, different CTE) to counteract the warpage caused by CTE mismatch in the original layered structure. This modifies the overall thermal-mechanical behavior of the package to maintain coplanarity during processing.
Solution Approach 2:
The patent creates a composite structure by embedding a reinforcement structure within the substrate layer. This composite approach combines the electrical functionality of the original substrate with the mechanical stability of the reinforcement material, achieving both electrical connectivity and coplanarity retention.
2Adaptability or versatility
If the semiconductor package includes multiple layers with different CTE (interposer, substrate, stiffener), then the electrical signal transmission is enabled, but thermal expansion mismatch causes warpage during surface mount process
Solution Approach 1:
The reinforcement structure acts as an intermediary element embedded within the substrate, mediating between the thermally expanding interposer/stiffener layers and the substrate itself. It provides mechanical anchoring and distributes thermal stresses to prevent warpage while allowing electrical signals to pass through the substrate.
Solution Approach 2:
The reinforcement structure is incorporated into the substrate before the surface mount process, providing pre-established mechanical support and stress distribution capability. This beforehand reinforcement cushions against the thermal expansion forces that will occur during subsequent heating in the surface mount process.
3Shape
If the substrate is made more rigid to reduce warpage, then coplanarity is maintained, but the flexibility and ease of manufacturing are reduced
Solution Approach 1:
Instead of making the entire substrate uniformly rigid, the patent applies the reinforcement structure locally within specific regions of the substrate where mechanical support is most needed to prevent warpage. This localized approach maintains coplanarity while preserving flexibility in other areas of the substrate for ease of manufacturing and assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reinforcement structure enhances the robustness of connection structures between the interposer and substrate, reducing the likelihood of electrical opens or shorts and improving the overall yield of the semiconductor package by maintaining coplanarity and reducing warpage during the surface mount process.
Implementation Method 1
the reinforcement structure is configured to improve a rigidity of the semiconductor package to reduce a warpage of the substrate
Implementation Method 2
mismatched coefficients of thermal expansion (CTE) between the interposer, substrate, and stiffener structure
Data Source
AI summary
Some implementations described herein provide techniques and apparatuses for a semiconductor package. The semiconductor package, which may correspond to a high performance computing package, includes a reinforcement structure that is embedded in a substrate of the semiconductor package. The reinforcement structure may increase a rigidity of the semiconductor package so that a warpage is reduced and a coplanarity between the substrate and a printed circuit board is maintained during a surface mount process. Reducing the warpage may increase a robustness of connection structures between an interposer and the substrate. Additionally, maintaining the coplanarity reduces a likelihood that connection structures at a bottom surface of the substrate will fail to adequately solder or attach to lands of the printed circuit board during the surface mount process. In this way, a likelihood of opens and/or shorts between the semiconductor package and the printed circuit board is reduced and a robustness of the semiconductor package may be increased to improve an overall yield of a product including the semiconductor package.