Processed Substrate Repair for Interconnect Erosion and Dishing
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Solution Overview
Problem
The dual damascene process for forming interconnect layers in semiconductor chips results in defects such as erosion and dishing, which lead to poor substrate surface flatness and reduced device yield.
Innovation Solution
A method involving selective etching using specific etchant formulations to address the erosion and dishing defects, allowing for the repair of substrates and the formation of pass-through conductive interconnections between substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual damascene process is used to form interconnect layers, then device density and yield are improved, but erosion and dishing defects occur reducing manufacturing precision
Solution Approach 1:
The patent applies preliminary action by performing selective etching of eroded regions and dished areas before subsequent processing steps. The method identifies and removes defective material in advance, then performs targeted deposition to restore surface topology, preventing defects from propagating to final devices.
Solution Approach 2:
The patent changes physical and chemical parameters by using selective etchants with different compositions and concentrations to treat different defect types. The process adjusts etching time, temperature, and chemical composition to selectively remove eroded metal regions and dished dielectric areas without affecting surrounding intact structures.
2Productivity
If high metal pattern density is used to improve device performance, then device density increases, but erosion defects worsen reducing reliability
Solution Approach 1:
The patent applies local quality by performing selective etching only in regions with eroded metal patterns, leaving intact regions unchanged. The process uses spatially selective treatment to restore local surface topology without affecting surrounding areas, maintaining high device density while improving local reliability.
3Productivity
If large metal structures are used to improve device performance, then device functionality is enhanced, but dishing defects increase reducing manufacturing precision
Solution Approach 1:
The patent performs preliminary removal of dished material from large metal structures before subsequent processing. By identifying and removing dished regions in advance, the method restores surface flatness while preserving the functional integrity of large metal interconnect structures.
4Ease of manufacture
If conventional planarization is used to remove unwanted conductive layers, then interconnect layers are formed, but dishing defects occur in large metal structures
Solution Approach 1:
The patent changes the approach from conventional planarization to selective etching by modifying process parameters. Instead of removing all material above a certain level, the method uses controlled etching to selectively remove only dished regions while preserving the topography of intact areas, thereby maintaining surface flatness without compromising interconnect formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively remedies substrate defects, improving surface flatness and interconnect reliability, thereby enhancing device yield and performance.
Implementation Method 1
The eroded surface of the substrate is selectively etched to cause interconnects to protrude above a reduced surface of the substrate
Implementation Method 2
The protruding conductive material is selectively etched by applying a second selective etchant to the conductive material
Data Source
AI summary
Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.