Substrate Routing Interconnects for High Density I/O Packages
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Solution Overview
Problem
Fabricating small packages with high density interconnects is challenging due to the need for compact designs that accommodate increased pin counts without increasing the overall size and form factor.
Innovation Solution
A package design featuring a substrate with inner and outer dielectric layers, routing interconnects located between solder interconnects, and a cover dielectric layer, which allows for efficient routing without increasing the package size by utilizing lateral space between solder interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional substrate interconnect routing is used, then the package can be fabricated with basic interconnect density, but the package size must increase to accommodate high pin counts and routing requirements
Solution Approach 1:
The patent applies dimensionality change by moving routing interconnects from the traditional planar substrate plane to the vertical dimension, placing them on the underside of the substrate between solder interconnects. This allows routing paths to extend into the third dimension, effectively increasing routing capacity without expanding the package footprint.
Solution Approach 2:
The routing interconnects are nested within the existing package structure by positioning them in the vertical space between the substrate and the solder interconnects. This nesting approach utilizes previously unused space within the package volume, allowing additional routing functionality without increasing external dimensions.
2Productivity
If more interconnects are added to increase pin count, then the package can support higher I/O density, but routing congestion increases and fabrication becomes more challenging
Solution Approach 1:
The patent segments the routing function by separating it from the traditional substrate interconnect layers. Routing interconnects are placed on the underside of the substrate in a distinct location, dividing the routing paths from the signal interconnects. This segmentation reduces routing congestion by providing dedicated routing space that does not interfere with the dense interconnect array.
Solution Approach 2:
The routing interconnects act as intermediary elements between the substrate and the external environment. By placing these routing paths on the underside of the substrate, they serve as a mediator that connects internal interconnects to external pads without interfering with the high-density interconnect routing within the substrate layers.
3Area of stationary object
If the package size is reduced for compact design, then the form factor improves, but there is insufficient space to accommodate high density interconnects and routing
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension for routing interconnects placed on the underside of the substrate. This dimensionality change allows the package to maintain a compact footprint while accommodating high interconnect density, as the routing paths extend into the vertical space that would otherwise be unused.
Solution Approach 2:
The substrate is utilized as a flexible structure that can accommodate interconnects on its top surface and routing interconnects on its underside. This flexible use of the substrate structure allows for high interconnect density in a compact package, as the substrate serves multiple functions across different surfaces and orientations.
Data Source
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AI summary
A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate.