Substrate Routing Layers With Through-Core Vias for Lower Insertion Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed integrated circuit (IC) device packages face challenges in reducing insertion loss while maintaining high data throughput, particularly due to the long route lengths of high-speed input/output signals, which are exacerbated by the high density of traces and limited void areas in the substrate, making it difficult to increase the distance between differential pair traces and the ground reference plane without increasing the layer count.
Innovation Solution
The solution involves selecting routing layers on both sides of the substrate core using through-core vias with mixed size and pitch, allowing signals to be routed on both front and backside layers, and utilizing multi-layer insulation structures to increase the distance between traces and the ground plane, thereby reducing insertion loss without increasing the layer count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traces are routed closer to the ground reference plane to reduce layer count, then manufacturing cost and complexity decrease, but insertion loss increases
Solution Approach 1:
The patent utilizes through-core vias to route high-speed signals from one side of the substrate core to the other side, enabling the use of routing layers on both sides of the core. This dimensional approach allows traces to be positioned on layers that adjoin multi-layer insulation structures, effectively increasing the distance between traces and the ground reference plane without increasing the overall layer count, thus reducing insertion loss while maintaining manufacturing efficiency
Solution Approach 2:
The substrate is divided into two separate metallization stacks (first and second metallization stacks) on opposite sides of the core structure. This segmentation allows independent optimization of routing layers on each side, enabling the use of through-core vias to connect signals across the core and utilize layers adjoining multi-layer insulation structures, thereby reducing insertion loss without compromising layer count
2Loss of energy
If the distance between differential pair traces and ground reference plane is increased to reduce insertion loss, then signal quality improves, but layer count must increase
Solution Approach 1:
By introducing through-core vias that penetrate the substrate core, the patent enables routing layers on both sides of the core to be utilized. This allows traces to adjoin multi-layer insulation structures on either side of the core, effectively increasing the trace-to-ground distance without adding layers in the vertical stacking direction, thus reducing insertion loss while maintaining the same layer count
Solution Approach 2:
The through-core vias serve multiple functions: they enable signal routing across the core, allow utilization of routing layers on both sides of the core, and facilitate connection to layers adjoining multi-layer insulation structures. This multi-functionality achieves insertion loss reduction without requiring additional layers
3Loss of energy
If through-core vias with mixed size and pitch are used to route signals on both sides of the core, then routing flexibility and insertion loss reduction are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs through-core vias with mixed size and pitch, where via dimensions and spacing are locally optimized based on specific routing requirements. This allows different regions of the substrate to have appropriately sized vias for their specific signal routing needs, achieving reduced insertion loss through optimized trace-to-ground spacing while managing manufacturing complexity through localized rather than uniform design
Data Source
AI summary
A substrate comprising a core structure between a first metallization stack and a second metallization stack. A hardware interface is at a side of the second metallization stack. A first interconnect comprises both a first via portion, and a first trace portion which extends from the first via portion in a first routing layer of the first metallization stack. The first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A second interconnect comprises both a second via portion, and a second trace portion which extends from the second via portion in the first routing layer. The second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A first multi-layer insulator structure adjoins respective sides of the first and second trace portions.