Package Substrate Selective Electroplating for Cost Reduction
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Solution Overview
Problem
The existing manufacturing process for package substrates results in a high cost due to the need to electroplate nickel and gold layers on the entire conductive layer, rather than just the portions corresponding to the semiconductor die's electrical contacts, leading to poor bonding force and increased expenses.
Innovation Solution
A package substrate design featuring a patterned dielectric layer with openings, allowing only specific portions of the wiring layer to be exposed and electroplated with nickel and gold, reducing unnecessary material usage and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nickel and gold layers are electroplated on the entire exposed conductive layer, then the bonding force between package substrate and semiconductor die is improved, but the manufacturing cost is significantly increased
Solution Approach 1:
The patent applies local quality by selectively electroplating nickel and gold layers only on specific portions of the conductive layer that correspond to semiconductor die electrical contacts, rather than the entire conductive layer. This is achieved through a mask layer that covers unnecessary areas during the electroplating process, thereby reducing material usage and cost while maintaining bonding force where needed.
2Reliability
If nickel and gold layers are electroplated on the entire exposed conductive layer, then the bonding force between package substrate and semiconductor die is improved, but the manufacturing cost is significantly increased
Solution Approach 1:
The patent applies local quality by selectively electroplating nickel and gold layers only on specific portions of the conductive layer that correspond to semiconductor die electrical contacts, rather than the entire conductive layer. This is achieved through a mask layer that covers unnecessary areas during the electroplating process, thereby reducing material usage and cost while maintaining bonding force where needed.
3Ease of manufacture
If the conductive layer is directly connected to the electrical contacts of the semiconductor die, then the manufacturing process is simplified, but the bonding force is poor and reliability is reduced
Solution Approach 1:
The patent applies composite materials by creating a multi-layer structure consisting of the conductive layer, mask layer, and selectively deposited nickel and gold layers. This composite structure provides both the electrical connectivity function of the conductive layer and the enhanced bonding force of the nickel-gold interface with semiconductor die electrical contacts, while the mask layer enables selective deposition to reduce cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost of nickel and gold layers by limiting their application to only the necessary areas, enhancing bonding force and reliability while maintaining circuit layout flexibility.
Implementation Method 1
a nickel layer and a gold layer are often electroplated on the conductive layer
Data Source
AI summary
A manufacturing method of a package substrate includes forming a patterned first dielectric layer on a carrier; forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing one of the openings of the first dielectric layer, and the carrier in one of the openings; forming a first conductive pillar layer on the first wiring layer on the first surface; forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer; forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; forming an electrical pad layer on the second wiring layer; and forming a third dielectric layer on the second dielectric layer and the second wiring layer.