Package Substrate Impedance Optimization for High-Speed SerDes
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Solution Overview
Problem
High-speed SerDes signal transmission faces challenges with significant substrate impedance discontinuity between BGA balls and C4 bumps, leading to increased differential return loss and degraded signal quality, especially at data rates above 25 Gb/s, where existing methods fail to maintain the desired differential impedance variation within ±10%.
Innovation Solution
The design incorporates specific structural features such as stacked and centered vias, adjusted PTH and via spacings, and optimized metal trace lengths and widths, along with strategic placement of ground planes and voids, to minimize impedance discontinuity, using a 3D full-wave electromagnetic simulation model for parameter optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional package substrate structures (BGA ball, via, PTH, trace, C4 bump) are used for high-speed SerDes signal transmission, then mechanical robustness and electrical interconnection are achieved, but significant impedance discontinuity occurs leading to increased differential return loss and degraded signal quality
Solution Approach 1:
The patent applies local quality by creating a localized ground plane structure specifically at the PTH region where impedance discontinuity occurs. The ground plane is positioned adjacent to the PTH and extends into the dielectric layer, providing localized electromagnetic field control and impedance matching exactly where needed, rather than uniformly across the entire substrate.
Solution Approach 2:
The ground plane acts as an intermediary element between the PTH and surrounding structures. It mediates the electromagnetic field distribution, providing a controlled reference potential that reduces impedance mismatch and signal reflections at the critical PTH transition zone.
2Speed
If the data rate is increased to 25 Gb/s and beyond, then transmission speed is improved, but substrate impedance discontinuity dramatically increases making it hard to meet differential return loss specifications
Solution Approach 1:
The patent changes geometric parameters of the ground plane structure (size, position, extension depth into dielectric layer) to optimize impedance control for high-speed signals. By adjusting these parameters, the ground plane effectively compensates for the increased impedance discontinuity that occurs at 25 Gb/s and beyond.
3Ease of manufacture
If simple approaches (increasing antipad diameter) are used to control impedance, then manufacturing is simplified, but these approaches are no longer effective at 25 Gb/s data rate and beyond to achieve desired differential impedance variation
Solution Approach 1:
Instead of only adjusting the antipad diameter in the horizontal plane, the patent extends the ground plane solution into the vertical dimension by positioning the ground plane within the dielectric layer adjacent to the PTH. This three-dimensional approach provides additional degrees of freedom for impedance control that simple two-dimensional antipad adjustments cannot achieve.
Data Source
AI summary
Package design method for semiconductor chip package for high speed SerDes signals for optimization of package differential impedance and reduction of package differential insertion loss and differential return loss at data rates of 25 to 60 Gb/s and beyond. The method optimizes parameters of vertical interconnections of BGA ball, via, and PTH, and around the joint between vertical and horizontal interconnections of traces. Also disclosed are examples of chip package designs for high speed SerDes signals, including one using 0.8 mm BGA ball pitch and IO-layer buildup substrate, one using 1 mm BGA ball pitch and 14-layer buildup substrate, one using 6-layer buildup substrate with signals routed on top and bottom metal layers with microstrip line structure, and one using 12-layer package substrate with unique via configuration, all of which achieve low substrate differential impedance discontinuity, reduced differential insertion loss and differential return loss between BGA balls and C4 bumps.