Semiconductor Substrate Gettering via Sessile Dislocations

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Solution Overview

Problem

Metal contamination in semiconductor devices reduces manufacturing yield and reliability by lowering the withstand voltage of the gate insulating film or generating leakage current, even in semiconductor bonded substrates.

Innovation Solution

A semiconductor substrate comprising a first and second semiconductor layer with a sessile dislocation composed of a stacking fault and a dislocation loop, with a density of 1E13/cm³ to 1E18/cm³, which acts as a metal getter to prevent contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a semiconductor bonded substrate is formed using conventional methods, then the substrate structure is established, but metal contamination reduces manufacturing yield and reliability

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmetal contamination
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The invention introduces controlled defects (sessile dislocations) into the semiconductor layer to convert the harmful effect of metal contamination into a beneficial gettering mechanism. These intentionally created dislocations act as traps that attract and immobilize metal impurities, preventing them from reaching active device regions and thereby improving device reliability despite the presence of contamination sources

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The sessile dislocations serve as intermediary trapping sites between the metal contamination sources and the device active regions. Instead of directly preventing contamination entry, the invention introduces these intermediate structures that capture metal atoms through their strained crystal fields, acting as a buffer zone that protects the device from harmful metal diffusion

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the withstand voltage of the gate insulating film is reduced due to metal contamination, then device performance deteriorates, but adding gettering structures increases device complexity

Engineering Contradiction:
Improvewithstand voltageVSAvoidsubstrate structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention applies local quality by creating sessile dislocations at specific locations and densities within the semiconductor layer rather than uniformly throughout. This localized defect engineering allows metal gettering to occur in specific regions while maintaining high crystal quality in device active areas, thereby protecting withstand voltage without requiring complex overall device redesign

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention changes the physical parameters of the semiconductor layer by controlling the density and distribution of sessile dislocations. By adjusting these defect parameters during crystal growth or post-processing, the substrate can be optimized to provide adequate metal gettering capacity while maintaining acceptable electrical properties and minimal impact on device complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The presence of sessile dislocations effectively gets metals, preventing a decrease in device yield and reliability due to poor voltage resistance or leakage current.

Implementation Method 1

at least one of a first semiconductor layer and a second semiconductor layer has a sessile dislocation composed of a stacking fault and a dislocation loop surrounding the stacking fault, and the density of the sessile dislocation is 1×10^13/cm³ or more... effectively gets metals

Methodology Applied
Scientific EffectGettering: Gettering

Implementation Method 2

sessile dislocation composed of a stacking fault and a dislocation loop surrounding the stacking fault... acts as a metal getter

Methodology Applied
Scientific EffectDislocation:

Data Source

PatentEP4636139A1Semiconductor substrate and method for producing semiconductor substrate
Publication Date: 2025.10.22 SUMITOMO METAL MINING CO LTD
  • EP4636139A1 patent drawingFigure 1~2
  • EP4636139A1 patent drawingFigure 3A~3B
  • EP4636139A1 patent drawingFigure 4

AI summary

Provided is a semiconductor substrate and a method for producing the semiconductor substrate that are resistant to metal contamination by gettering metals that cause metal contamination. A semiconductor substrate comprising a first semiconductor layer and a second semiconductor layer in contact with the first semiconductor layer, wherein at least one of the first semiconductor layer and the second semiconductor layer has a sessile dislocation composed of a stacking fault and a dislocation loop surrounding the stacking fault, and the density of the sessile dislocation is 1E13/cm3 to 1E18/cm3.