Semiconductor Substrate Stress Testing via Patterned Nitride Dislocations
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Solution Overview
Problem
Existing stress tests for semiconductor substrates cause mechanical damage and provide localized information, failing to simulate the device manufacturing process effectively.
Innovation Solution
A method involving the formation of a nitride layer on the substrate, patterning it, and subjecting it to thermal treatment to induce dislocations, allowing evaluation of stress robustness without mechanical indentation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an indenter test is used to test stress robustness, then mechanical damage is introduced to the substrate, but this causes deep crystal lattice damage and plastic deformation that is untypical for actual device processes
Solution Approach 1:
The patent replaces the mechanical indenter system with a chemical deposition system. Instead of using physical indentation to create stress, the invention deposits a nitride layer that generates stress through thermal expansion mismatch and intrinsic film stress during subsequent thermal processing. This substitution eliminates mechanical damage while still inducing dislocations for robustness testing.
Solution Approach 2:
The patent changes the testing parameters from mechanical force application to thermal processing parameters. By controlling deposition temperature, thermal processing temperature (800-1300°C), and nitride layer thickness, the method induces controlled stress and dislocation formation without mechanical impact, thereby avoiding plastic deformation while maintaining testing reliability.
2Measurement precision
If an indent test is used, then localized information on substrate properties is obtained, but this does not provide information over the full semiconductor wafer
Solution Approach 1:
The patent creates a universal testing method that can evaluate the entire wafer surface simultaneously. By depositing a nitride layer across the full wafer area and performing thermal processing, the method generates stress fields throughout the entire substrate, enabling comprehensive evaluation of stress robustness across all regions rather than仅限于 localized indent points.
Solution Approach 2:
The patent transitions from one-dimensional localized testing (single indent point) to two-dimensional full-wafer testing. The nitride layer deposition and thermal processing create stress fields that extend across the entire wafer surface, adding spatial dimensionality to the testing approach and enabling simultaneous evaluation of multiple regions.
3Productivity
If advanced device processing with 3D structures and extreme heat treatments is performed, then device performance is improved, but localized stress fields and mechanical damage are induced
Solution Approach 1:
The patent performs preliminary stress robustness testing before actual device manufacturing. By depositing the nitride layer and conducting thermal processing on test structures or sacrificial areas, the method evaluates substrate robustness in advance, allowing selection of substrates that can withstand subsequent extreme heat treatments and 3D processing without suffering mechanical damage.
Solution Approach 2:
The patent uses the nitride layer as a protective and testing mechanism before device processing. The layer serves as a cushion that allows controlled stress induction for testing purposes, enabling evaluation of substrate resilience before committing to actual device manufacturing processes that would be damaged by such stress induction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Provides a realistic simulation of device manufacturing processes, identifying substrates with improved mechanical robustness and reducing dislocation formation, enhancing yield in high-volume production.
Implementation Method 1
forming a nitride layer on a surface of the semiconductor substrate, the nitride layer being directly deposited on the surface of the semiconductor substrate
Implementation Method 2
processing the patterned nitride and the semiconductor substrate at a temperature of not less than 800° C. and not more than 1300° C. in a nitrogen atmosphere to induce the formation of dislocations at an interface between the patterned nitride and the semiconductor substrate
Implementation Method 3
patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions produced from a gas which includes hydrogen or a hydrogen compound or both
Data Source
AI summary
A method tests the stress robustness of a semiconductor substrate. The method includes: forming a nitride layer on a surface of the semiconductor substrate, the nitride layer being directly deposited on the surface of the semiconductor substrate or on a native oxide layer that is interposed on the surface; cooling the semiconductor substrate and the nitride layer; patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions produced from a gas, which includes hydrogen or a hydrogen compound or both; processing the patterned nitride and the semiconductor substrate at a temperature of not less than 800° C. and not more than 1300° C. in a nitrogen atmosphere to induce the formation of dislocations at an interface between the patterned nitride and the semiconductor substrate; and evaluating at least one property that is related to the formed dislocations.