Substrate Tab Interconnect Assembly for Compact Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
The proposed solution involves a semiconductor assembly method where a first semiconductor device and a second semiconductor device are connected through a substrate tab with an exposed conductive structure, using a dielectric material to encapsulate components while maintaining electrical connectivity via an interconnect, and employing pre-formed substrates with dielectric and conductive layers to form a compact and reliable package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing is simpler, but cost is high and reliability is decreased
Solution Approach 1:
The substrate is divided into multiple substrate tabs, each serving as an independent connection point. This segmentation allows for modular assembly and improved reliability through distributed connections, while the standardized tab design maintains manufacturing simplicity
Solution Approach 2:
The patent transitions from planar package layouts to three-dimensional stacked configurations with substrate tabs extending in multiple directions. This dimensional change enables compact packaging with improved electrical connectivity and reliability without significantly increasing manufacturing complexity
2Volume of moving object
If conventional semiconductor packages are used, then manufacturing is simpler, but package size is large and performance is low
Solution Approach 1:
Multiple semiconductor devices are nested within a compact package structure, with substrate tabs providing hierarchical interconnection. This nesting approach dramatically reduces package volume while the modular tab design keeps manufacturing complexity manageable
Solution Approach 2:
The package architecture utilizes vertical stacking and three-dimensional routing through substrate tabs, transforming traditional two-dimensional layouts into compact three-dimensional structures that reduce overall package size while maintaining ease of manufacture through standardized processes
3Productivity
If conventional packages are used, then design is simpler, but electrical connection efficiency is low
Solution Approach 1:
The electrical connection system is segmented into multiple substrate tabs that provide parallel current paths. This segmentation increases connection efficiency by distributing electrical load across multiple independent pathways, while each individual tab maintains simple construction
Solution Approach 2:
Electrical connections transition from planar traces to three-dimensional conductive pathways through substrate tabs. This dimensional change enables shorter current paths and improved signal integrity, achieving higher connection efficiency without excessive structural complexity
Data Source
AI summary
In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.