Substrate Outward Terminal Structure to Reduce Package Cracking
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Solution Overview
Problem
Existing semiconductor packages face issues such as excess cost, decreased reliability, relatively low performance, and large package sizes due to inadequate design and manufacturing methods.
Innovation Solution
The use of a substrate with a substrate outward terminal that includes a multi-via terminal or a multi-stage terminal, which reduces stress-related issues like cracks by minimizing the size of dimples formed in the terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional substrate terminal design is used, then the package size can be larger, but stress-related cracks occur more frequently and reliability decreases
Solution Approach 1:
The substrate terminal is divided into multiple segments (first terminal segment, second terminal segment, third terminal segment) arranged in a staggered configuration. This segmentation distributes the mechanical stress across multiple smaller contact points rather than concentrating it in a single large terminal, thereby reducing stress-related cracks and improving reliability.
2Reliability
If a multi-via terminal structure is implemented, then cracking likelihood is reduced, but device complexity increases
Solution Approach 1:
The terminal structure employs a nested via configuration where multiple vias are stacked vertically and connected through conductive layers. The first, second, and third terminal segments are nested within the substrate thickness, with each segment connected to the next through vias. This nesting approach reduces the lateral footprint and distributes stress vertically, improving crack resistance while maintaining a compact structure.
3Reliability
If substrate outward terminals are optimized to reduce dimple size, then stress is reduced and reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The terminal structure incorporates localized features including pad dielectric vias with specific depth ranges (5-20 micrometers) and controlled dimple formations at terminal intersections. The staggered terminal segments create localized stress distribution zones rather than uniform stress across the entire terminal. This local quality control allows stress reduction through optimized dimple characteristics while maintaining manufacturability through controlled local features rather than requiring precision across the entire structure.
Data Source
AI summary
An electronic device includes a substrate having a conductive structure with a substrate outward terminal at a second side of the substrate. A dielectric structure with an opening is adjacent to the second side. An electronic component is coupled to the substrate and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the opening, a pad dielectric via interposed between the pad conductive vias, and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via. The multi-stage terminal includes a pad base within the opening having a top side recessed below an upper surface the dielectric and a pad head coupled to the pad base within the opening, the pad head having a top side with a micro dimple.