Semiconductor Substrate Testing Before Backside Circuit Fabrication
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Solution Overview
Problem
The high cost of fabricating back side circuitry in semiconductor devices is wasteful if the front side circuitry has defects, as the entire process is expensive and cannot be reused.
Innovation Solution
A methodology is proposed where the front side circuitry of a semiconductor substrate is first formed and tested before proceeding to form the back side circuitry, with defective substrates being discarded if the front side circuitry fails testing, thereby optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If back side circuitry is fabricated without prior testing of front side circuitry, then manufacturing throughput is improved, but resource waste increases due to defective substrates
Solution Approach 1:
The patent implements preliminary testing of the front side circuitry before proceeding to fabricate the back side circuitry. This preliminary action allows identification and discarding of defective substrates early in the process, preventing waste of resources on substrates that would ultimately fail. The testing step is inserted between front side fabrication and back side fabrication to catch defects before they propagate through the entire manufacturing process.
2Loss of substance
If front side circuitry is tested before back side fabrication, then resource utilization is improved, but manufacturing time increases due to additional testing steps
Solution Approach 1:
The patent converts the potential harm of extended manufacturing time into a benefit by demonstrating that the additional testing time prevents much larger resource waste. The brief testing interval acts as a small investment that saves substantial materials, equipment usage, and subsequent processing time that would be wasted on defective substrates. The net effect is a reduction in total manufacturing time when accounting for rework and waste prevention.
Data Source
AI summary
A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.