Substrate Testing Circuit Segmentation Equalizes Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing substrate testing circuits for LCDs face issues with non-uniform voltage distribution and signal attenuation due to high resistance in lead lines, particularly in large-size panels, leading to degraded test results.
Innovation Solution
The introduction of multiple signal access terminals connected to a testing bus with testing branches of equal resistance values, which averages input resistances and impedances across the display screen, preventing regional signal attenuation and allowing testing of larger panels without altering the process flow or hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a testing circuit is integrated on the glass substrate with lead lines connecting testing signal terminals to pixel areas, then the testing circuit can be implemented, but the resistance of the lead lines causes voltage dividing effect and RC delay effect leading to signal attenuation and non-uniform voltage distribution
Solution Approach 1:
The testing bus is segmented into multiple sections with multiple signal access terminals distributed at different locations. Each section has a testing branch connecting to a corresponding signal line, dividing the long lead line into shorter segments. This segmentation reduces the resistance and RC delay effect in each segment while maintaining the overall testing function.
Solution Approach 2:
Different locations on the testing bus are equipped with different numbers of signal access terminals based on local requirements. The testing branches are designed with equal resistance values to compensate for the varying distances and resistances at different locations, ensuring uniform voltage distribution across the entire display screen.
2Adaptability or versatility
If the number of signal lines is increased to cover more pixel areas, then the testing coverage is improved, but the length of the testing bus increases significantly causing greater voltage drop and non-uniform signal voltages
Solution Approach 1:
The testing bus is divided into multiple sections with signal access terminals distributed at different locations. Each section serves a specific pixel area, allowing the system to scale testing coverage by adding more sections rather than extending a single long bus, thereby maintaining voltage uniformity.
Solution Approach 2:
The testing branches are designed with equal resistance values to ensure that all signal lines receive uniform voltage despite varying distances from the testing signal terminals. This equipotential design compensates for the voltage drop effect and maintains consistent signal voltages across all pixel areas regardless of the number of signal lines.
3Reliability
If the resistance of the testing bus is reduced to minimize voltage drop, then signal attenuation is reduced, but the complexity of the testing circuit increases due to additional testing branches and access terminals
Solution Approach 1:
The testing bus is segmented into multiple sections with distributed signal access terminals. Each segment has a dedicated testing branch with equal resistance, which simplifies the design by using identical modular units rather than requiring complex impedance matching across the entire bus. This segmentation reduces signal attenuation while maintaining manageable circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures uniform signal voltages and reduced attenuation, enabling effective testing of larger panels with improved contact reliability and reduced production time.
Implementation Method 1
resistances of the lead lines of the testing circuit integrated on the glass substrate are great, when the above testing circuit is applied to a large size LCD, an obvious attenuation occurs in the testing signals
Implementation Method 2
a part of voltage is consumed over the data testing even bus 22, such that a signal voltage measured on a data line 2 far away from the data testing even terminal DE must be relatively low
Implementation Method 3
resistance-capacitance delay (RC Delay) effect of the resistance of the lead lines, such that testing signals are too low in some parts of the display screen
Data Source
AI summary
The present invention relates to a substrate testing circuit comprising a testing bus and a testing signal terminal connected to the testing bus, a signal line to be tested in the substrate being connected to the testing bus via a signal connecting terminal, wherein a plurality of signal access terminals are provided on the testing bus; one testing branch is connected between each the signal access terminal and the testing signal terminal; and resistance values of the testing branches are the same. By means of the present invention, since a plurality of signal access terminals are introduced and the testing branches with the same resistance are added so that input resistances and impedances of testing signals across the display screen are substantially identical without making changes to process flow and device hardware structure, input resistances and impedances of respective signal lines are well averaged, thereby no obvious regional attenuation occurs in the testing signals within the pixel area to be tested irrespective of limitation in size of panel, so as to realize tests for panels with greater sizes.