Package Substrate Testing Pads for Fine Pitch Alignment
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Solution Overview
Problem
Testing package substrates with fine pitch traces is challenging due to misalignment issues during testing, which can lead to improper testing and increased errors, especially when pins of a testing device are not aligned with the traces on the substrate.
Innovation Solution
A package substrate design that includes a solder resist layer covering the traces, with exposed portions for chip connection and additional testing pads that are partially exposed and free of the solder resist layer, allowing for accurate alignment and connection with testing pins, and having a width larger than the traces to ensure proper coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pitch traces (100 microns or less) are used on the substrate to increase chip density, then the chip density and integration are improved, but misalignment occurs when testing pins are connected to the traces during testing
Solution Approach 1:
The patent divides the trace structure into multiple segments by adding testing pads at intermediate locations along the traces. This segmentation allows testing pins to connect to larger testing pads rather than attempting to align with the entire fine pitch trace, thereby resolving the alignment accuracy problem while maintaining the fine pitch trace configuration for high chip density.
Solution Approach 2:
The testing pads serve as intermediary elements between the fine pitch traces and the testing pins. These pads provide a larger target area that mediates the connection process, making it easier for testing pins to achieve proper alignment without directly requiring precise alignment with the narrow fine pitch traces themselves.
2Length of moving object
If the trace width is kept small to maintain fine pitch, then the chip density is improved, but the testing pins cannot be properly aligned and connected to the traces
Solution Approach 1:
The patent segments the narrow trace into multiple sections by introducing testing pads at intermediate points. This allows the trace to maintain its narrow width for high density while the testing pads provide larger connection areas that ease the testing operation.
Solution Approach 2:
The patent extends the connection interface from the narrow trace dimension to a two-dimensional testing pad structure. By adding pads that traverse through the substrate and provide larger surface areas, the connection ease is improved without increasing the trace width, effectively moving the solution to another dimensional space.
3Measurement precision
If testing pads are added at intermediate locations on the traces, then testing alignment accuracy is improved, but the device complexity increases
Solution Approach 1:
The testing pads serve multiple functions: they provide alignment targets for testing pins, maintain electrical connection to the fine pitch traces, and can also serve as bonding locations. This multi-functionality reduces the need for separate dedicated testing structures, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the testing function with the existing trace structure by integrating testing pads into the trace network. Rather than adding completely separate testing infrastructure, the pads are combined with the signal traces, reducing overall structural complexity while still improving testing alignment accuracy.
Data Source
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AI summary
Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (m) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.