Device Substrate Thermal Via Stack for Package Heat Dissipation
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Solution Overview
Problem
Existing heat dissipation solutions for semiconductor devices are limited by the size of the silicon die and the thermal resistance of thermal interface materials, which hinder efficient heat conduction from the device to the heat sink.
Innovation Solution
A device substrate with a vertically stacked thermal conduction structure comprising metal lines and vias under a redistribution layer, isolated from electrical routing structures, provides a direct thermal conduction path to a heat spreader, enhancing heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional heat dissipation solutions are used through thermal interface materials, then heat conduction from device to heat sink is achieved, but thermal resistance is high and heat dissipation efficiency is limited
Solution Approach 1:
The patent segments the heat dissipation function by separating thermal conduction paths from electrical routing structures. The interconnect structure is divided into distinct thermal conduction structures (dedicated vertical vias and metal lines) that are electrically isolated from signal routing, allowing optimized thermal management without interfering with electrical performance.
Solution Approach 2:
The patent transitions from planar heat dissipation to three-dimensional vertical heat conduction by implementing stacked levels of dielectric layers and conductive connectors. The thermal conduction structures extend vertically through multiple intermetal dielectric layers, creating a direct path from the device layer through the interconnect structure to the heat spreader, significantly reducing thermal resistance.
2Productivity
If feature size is decreased to increase functional density, then production efficiency improves and costs decrease, but heat dissipation becomes more challenging due to smaller die size
Solution Approach 1:
The patent addresses heat dissipation challenges in high-density integration by moving from two-dimensional lateral heat spreading to three-dimensional vertical heat conduction. The stacked interconnect structure provides direct vertical thermal pathways that efficiently conduct heat away from the high-density device layer, maintaining effective heat dissipation even as die size decreases and functional density increases.
Solution Approach 2:
The patent introduces thermal conduction structures as intermediary elements between the high-density device layer and the heat spreader. These dedicated thermal pathways act as mediators that efficiently transfer heat from the compact, high-density integrated circuits to the heat dissipation system, overcoming the thermal management challenges posed by miniaturization.
3Device complexity
If thermal conduction structures are integrated with electrical routing structures, then device complexity is reduced, but electrical interference and signal integrity issues arise
Solution Approach 1:
The patent segments the interconnect structure into functionally distinct components: thermal conduction structures and electrical routing structures. The thermal conduction structures consist of vertically stacked vias and metal lines that are electrically isolated from signal routing by being surrounded by dielectric material, thereby preventing electrical interference while maintaining structural integration.
Solution Approach 2:
The patent uses dielectric layers as intermediary materials that electrically isolate the thermal conduction structures from electrical routing structures. This segmentation allows both functions to coexist within the same interconnect structure without electrical interference, maintaining signal integrity while providing integrated thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively alleviates the heat dissipation issue by providing a direct thermal conduction path from integrated circuits to the package substrate, improving thermal conductivity and reducing thermal resistance.
Implementation Method 1
A device substrate with a vertically stacked thermal conduction structure comprising metal lines and vias under a redistribution layer, isolated from electrical routing structures, provides a direct thermal conduction path to a heat spreader, enhancing heat dissipation.
Data Source
AI summary
A method for forming a device substrate is provided. The method includes forming a device layer on a semiconductor substrate, forming an interconnect structure over the device layer, and forming a redistribution layer over the interconnect structure. The interconnect structure includes stacked levels of dielectric layers and conductive connectors in the respective dielectric layers. The conductive connectors are divided into groups. The conductive connectors in a first group are connected to one another. The redistribution layer includes a first conductive pad connected to the first group of conductive connectors. The method further includes forming a polymer layer over the redistribution layer, and patterning the polymer layer to form a first opening partially exposing a first conductive pad. In a plan view, a dimension of the first group of conductive connectors is less than a dimension of the first opening.