Circuitized Substrate Transversal Supply Module
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Solution Overview
Problem
Current circuitized substrates face challenges in providing sufficient capacitance for power supply stability due to limited integration of decoupling capacitors, which increases costs and degrades performance, especially in flip-chip electronic devices where capacitors are either small, integrated on the chip, or mounted on carriers with high line inductance and series resistance.
Innovation Solution
A circuitized substrate design featuring a supply module with conductive elements and insulating elements crossing transversally to house auxiliary components like capacitors close to the chip, reducing line inductance and series resistance, and allowing for high capacitance density without the need for special integration technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are integrated on the chip, then capacitance is provided, but manufacturing complexity and cost increase due to special integration technologies
Solution Approach 1:
The patent extracts the capacitors from the chip itself and places them on the carrier substrate. This eliminates the need for complex deep trench integration technologies while maintaining capacitance functionality. The capacitors are mounted on the carrier surface and connected through conductive vias, simplifying the overall manufacturing process.
Solution Approach 2:
The patent introduces a carrier substrate as an intermediary between the chip and the external environment. The carrier hosts the capacitors and provides conductive vias for connection, acting as a mediator that simplifies both chip integration and external connectivity while reducing manufacturing complexity.
2Quantity of substance
If capacitors are mounted on the carrier, then capacitance is provided, but line inductance and series resistance increase due to distance from chip
Solution Approach 1:
The patent utilizes the vertical dimension by implementing through-via connections that extend perpendicular to the chip surface. This three-dimensional routing approach reduces the horizontal distance and inductance while maintaining capacitor functionality, effectively moving the connection path from a planar to a spatial dimension.
3Quantity of substance
If capacitors are mounted on the carrier, then capacitance is provided, but available mounting area is limited
Solution Approach 1:
The patent exploits the vertical space above the chip by mounting capacitors on the carrier surface and using through-via connections. This three-dimensional arrangement allows larger capacitors to be positioned closer to the chip without occupying additional planar area, effectively utilizing the Z-dimension to increase capacitance density.
Data Source
AI summary
A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.