Semiconductor Package Substrate Vent Hole for Void Removal
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Solution Overview
Problem
In semiconductor packages, wire bonding can lead to disconnection issues during molding and limits package thickness due to wire length and configuration, prompting the need for alternative connection methods like flip chip bonding to enhance reliability and reduce signal transfer paths.
Innovation Solution
A semiconductor package structure featuring a substrate with a vent hole, a semiconductor chip mounted on the upper surface, solder ball pads on the lower surface, and an encapsulant covering the substrate except for the solder ball pads, allowing for the removal of voids near the chip and reducing package thickness through efficient encapsulant flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect semiconductor chip and substrate, then electrical connections can be established, but wires may be disconnected during molding and package thickness cannot be reduced due to wire length constraints
Solution Approach 1:
The patent replaces wire bonding (mechanical wire connection) with flip chip bonding (direct solder ball connection). The semiconductor chip is flipped and bonded directly to the substrate using solder balls, eliminating the need for long wires that constrain package thickness. This substitution of connection mechanism resolves both the reliability issue (no wire disconnection) and the thickness issue (direct connection enables thinner packages).
Solution Approach 2:
The patent inverts the conventional chip orientation by flipping the semiconductor chip upside down for bonding. Instead of bonding the chip's upper surface to the substrate (conventional method), the chip is flipped and its lower surface with solder balls is bonded directly to the substrate. This inversion enables direct electrical connection through solder balls, eliminating wire bonding constraints on package thickness and improving reliability.
2Reliability
If encapsulant is formed to cover the substrate and chip, then protection is provided, but voids may be trapped near the lower portion of the chip
Solution Approach 1:
The patent extracts air from the encapsulation region by forming vent holes through the substrate. These vent holes provide escape paths for air bubbles during the encapsulant filling process, allowing trapped air to be extracted and vented out. This prevents void formation in the final packaged product, improving reliability without compromising the protective function of the encapsulant.
Solution Approach 2:
The patent introduces vent holes as intermediary structures that mediate between the encapsulant filling process and the trapped air. The vent holes serve as controlled channels that allow air to escape systematically during encapsulant injection, preventing random void formation. This intermediary structure enables complete encapsulation while eliminating the harmful effect of trapped air bubbles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of semiconductor packages by removing voids and reducing thickness, enhancing electrical signal transfer and package reliability while avoiding limitations of wire bonding.
Implementation Method 1
an encapsulant covering an entirety of the first and second non-connection regions and the semiconductor chip
Data Source
AI summary
A semiconductor package includes a substrate having a vent hole extending through the substrate, a semiconductor chip mounted on an upper surface of the substrate, a plurality of solder ball pads formed on a lower surface of the substrate, and an encapsulant covering the upper surface of the substrate, the semiconductor chip, and an entirety of the lower surface of the substrate except for regions in which the solder ball pads are formed.