Semiconductor Substrate Via Geometry for Smaller Via Lands
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Solution Overview
Problem
In semiconductor device packages, the size of via lands is often affected by manufacturing recesses or protrusions, leading to structural issues and increased package size, as existing solutions to create a flat surface for subsequent structures can enlarge the package unnecessarily.
Innovation Solution
A substrate design with conductive vias of varying widths, where the end of one via is narrower than the opposite end, allowing for a smaller via land and reduced pitch in patterned conductive layers, thereby improving electrical connections and avoiding voids or cracks at interfaces between stacked vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the via land is expanded to have a relatively flat or smooth surface to receive subsequent structures, then the structural integrity and manufacturing quality improve, but the size of the semiconductor device package increases
Solution Approach 1:
The patent applies asymmetry by designing the conductive via with different widths at opposite ends (first end width < second end width). This asymmetric via shape allows the via land to be smaller while still providing sufficient flat surface area for subsequent structures, thereby reducing package size while maintaining manufacturing quality.
Solution Approach 2:
The patent applies local quality by creating a via land with a first region that has a first width and a second region that has a second width greater than the first width. This localized variation in width provides the necessary flat surface area in the second region for receiving subsequent structures, while the overall via land size is reduced compared to a uniformly expanded via land.
2Area of stationary object
If the via land size is reduced to minimize package size, then the compactness improves, but manufacturing defects such as voids or cracks may occur at interfaces between stacked vias
Solution Approach 1:
The asymmetric via design (different widths at opposite ends) creates an optimized via land geometry that maintains sufficient area for reliable electrical connections and structural integrity, while minimizing the overall package size. The wider second end provides adequate surface area to prevent voids or cracks.
Solution Approach 2:
The via land with varying width (narrower first region, wider second region) locally increases the surface area at the second region where it is most needed for reliable connections, while keeping the overall via land size compact. This localized expansion prevents manufacturing defects without unnecessarily increasing package size.
3Productivity
If the pitch in patterned conductive layers is reduced to increase device density, then the device complexity and functionality improve, but the manufacturing precision requirements increase
Solution Approach 1:
The asymmetric via shape provides an optimized geometry that allows for reduced pitch between adjacent vias while maintaining manufacturing feasibility. The varying width profile creates natural clearance zones that facilitate precise manufacturing even at reduced pitch.
Solution Approach 2:
The via land with localized width variation provides optimized clearance and spacing characteristics that enable reduced pitch in patterned conductive layers. The wider second region provides sufficient manufacturing tolerance buffer, allowing tighter pitch control while maintaining reliability.
Data Source
AI summary
A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.