Substrate Void Preventing Patterns for Underfill Reliability
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Solution Overview
Problem
The integration of wire-bonding technology in semiconductor packaging leads to increased complexity due to high wire integration levels, and the flipchip bonding process using brittle solder bumps is susceptible to shock, often resulting in void formation under chips due to uneven underfill material distribution.
Innovation Solution
A semiconductor package design featuring a substrate with void-preventing patterns on its surface, which are formed on a solder resist layer and protrude to guide the underfill material effectively, preventing voids by ensuring even distribution and encapsulating solder bumps, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding technology is used to connect chips to substrate, then electrical connection is achieved, but wire integration level increases making the packaging process difficult
Solution Approach 1:
The patent extracts the wiring function from traditional wire-bonding and relocates it to the substrate level by forming conductive patterns directly on the substrate. This eliminates complex wire integration while maintaining electrical connection functionality, resolving the contradiction between connection reliability and packaging complexity.
2Device complexity
If flipchip bonding process is used to directly connect solder bumps to substrate, then wire integration complexity is reduced, but solder bumps are susceptible to shock and may form voids
Solution Approach 1:
The patent introduces an underfill material as an intermediary substance between the solder bumps and substrate. This underfill material fills the gaps and provides mechanical support, acting as a mediator that protects the brittle solder bumps from shock while preventing void formation, thus resolving the reliability issue without sacrificing the simplified packaging process.
3Ease of manufacture
If underfill material is dispensed using capillary effect, then underfill region is formed, but movement of underfill material is retarded by solder bumps causing voids
Solution Approach 1:
The patent applies preliminary action by pre-forming protrusions on the substrate surface at strategic locations before dispensing the underfill material. These protrusions guide the capillary flow of the underfill material, preventing it from being retarded by solder bumps and ensuring uniform distribution, thus resolving the contradiction between ease of manufacture and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents void formation under chips, improving the reliability and durability of semiconductor packages by ensuring uniform underfill material distribution and mechanical stress reduction.
Implementation Method 1
The underfill region can be formed by filling a lower portion of the chip with a liquid type underfill material using a capillary effect by dispensing the liquid underfill material to a chip side.
Data Source
AI summary
Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer.