Substrate Wafer Internal Ducts for Processor Heat Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in microelectronics is the heat generated by processor chips degrading the performance of stacked memory chips due to thermal issues, which limits the performance and footprint compromise, especially in portable devices like mobile phones.
Innovation Solution
An electronic device with a substrate wafer made of insulating material, equipped with an electrical connection network and internal ducts filled with thermally conductive material, which directs heat away from the electrical connections and disperses it throughout the substrate and to external cooling systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electronic devices are stacked one on top of the other to improve connection performance and reduce footprint, then electrical connection performance is improved and footprint is reduced, but heat from processor chips degrades memory chip performance
Solution Approach 1:
The substrate wafer is segmented into multiple functional layers including insulating material layers and conductive trace layers, allowing separate thermal and electrical management paths. The thermal vias are segmented throughout the substrate to create distributed heat dissipation channels that prevent heat accumulation at memory chip locations.
Solution Approach 2:
The substrate wafer acts as an intermediary between the processor chip and memory chip, providing both electrical connection and thermal management functions. The conductive traces and thermal vias within the substrate serve as intermediary heat transfer paths, conducting heat away from the processor chip while isolating the memory chip from excessive heat through strategic placement and insulation layers.
2Area of stationary object
If electronic devices are stacked one on top of the other to reduce footprint, then footprint is reduced, but heat from processor chips degrades memory chip performance
Solution Approach 1:
The invention transitions from two-dimensional planar layout to three-dimensional stacked architecture with vertical heat dissipation paths. Thermal vias extend vertically through the substrate wafer, creating a third dimension for heat management that allows compact footprint while maintaining thermal performance through depth-based heat extraction.
Solution Approach 2:
The substrate wafer is segmented into multiple functional layers including insulating material layers and conductive trace layers, allowing separate thermal and electrical management paths. The thermal vias are segmented throughout the substrate to create distributed heat dissipation channels that prevent heat accumulation at memory chip locations.
3Power
If processor chip produces heat to maintain performance, then processing capability is maintained, but heat degrades memory chip operation
Solution Approach 1:
Heat is extracted from the processor chip through the substrate wafer before it can reach the memory chip. The conductive traces and thermal vias extract thermal energy from the processor chip location, and the insulating layers prevent this extracted heat from transferring to the memory chip, effectively taking the harmful thermal component out of the system.
Solution Approach 2:
The substrate wafer acts as an intermediary between the processor chip and memory chip, providing both electrical connection and thermal management functions. The conductive traces and thermal vias within the substrate serve as intermediary heat transfer paths, conducting heat away from the processor chip while isolating the memory chip from excessive heat through strategic placement and insulation layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively cools processor chips by transferring heat to the substrate and then to the printed circuit board, preventing excessive temperature increase in adjacent memory chips and enhancing system performance without increasing footprint.
Implementation Method 1
Said internal duct may contain a thermally conductive material
Implementation Method 2
The substrate wafer may comprise, on this internal plane, an intermediate layer covered by said superficial layer and in which said groove is arranged... connected to means for making a fluid flow
Data Source
AI summary
An electronic device includes a substrate wafer made of an insulating material and having an electrical connection network. An integrated circuit chip is mounted to a top side of the substrate wafer. The substrate wafer contains an internal duct. The duct is formed by a covered trench located in the top side of the substrate wafer. The trench contains a thermally conductive material, for example being a fluid. Openings in the top side of the substrate wafer that are offset from the trench permit the making of an electrical connection between the integrated circuit and the electrical connection network.