Stacked Semiconductor Package Substrate Zoning for CTE Mismatch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in maintaining reliability and reducing size due to thermal expansion coefficient mismatches between different regions, leading to warpage failures and potential damage to semiconductor dies.
Innovation Solution
A semiconductor package design with a first substrate divided into regions of differing thermal expansion coefficients, featuring varying metal pattern densities and widths, and a stepwise die stacking structure, along with vertical conductive lines and mold layers to manage thermal expansion variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform substrate structure is used, then manufacturing is simple, but thermal expansion coefficient differences cause warpage failures
Solution Approach 1:
The substrate is divided into multiple regions with different metal pattern densities, creating local variations in thermal expansion coefficients. Each region has tailored metal pattern characteristics (density, width, spacing) to compensate for thermal expansion differences in specific areas, thereby reducing overall warpage while maintaining manufacturing feasibility through systematic pattern design.
2Reliability
If metal pattern density is increased, then thermal expansion compensation improves, but manufacturing complexity increases
Solution Approach 1:
The substrate is segmented into multiple regions, each with distinct metal pattern densities and configurations. This segmentation allows thermal expansion compensation to be optimized locally in each region without requiring complex patterns across the entire substrate, thereby improving thermal management while keeping individual region patterns relatively simple and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces thermal expansion coefficient differences, minimizing warpage failures and enhancing the reliability of the semiconductor package by compensating for thermal expansion disparities.
Implementation Method 1
The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.
Data Source
AI summary
A semiconductor package may include a first substrate, semiconductor dies stacked on the first substrate in a direction perpendicular to a top surface of the first substrate to have a stepwise structure, a mold layer disposed on the first substrate to cover the semiconductor dies, a second substrate disposed on the mold layer, and vertical conductive lines electrically connecting the semiconductor dies to the second substrate. The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.